Home
last modified time | relevance | path

Searched refs:uint32_t (Results 1 – 25 of 4014) sorted by relevance

12345678910>>...161

/openbmc/linux/drivers/gpu/drm/amd/include/
H A Dv11_structs.h28 uint32_t shadow_base_lo; // offset: 0 (0x0)
29 uint32_t shadow_base_hi; // offset: 1 (0x1)
30 uint32_t gds_bkup_base_lo; // offset: 2 (0x2)
31 uint32_t gds_bkup_base_hi; // offset: 3 (0x3)
32 uint32_t fw_work_area_base_lo; // offset: 4 (0x4)
33 uint32_t fw_work_area_base_hi; // offset: 5 (0x5)
34 uint32_t shadow_initialized; // offset: 6 (0x6)
35 uint32_t ib_vmid; // offset: 7 (0x7)
36 uint32_t reserved_8; // offset: 8 (0x8)
37 uint32_t reserved_9; // offset: 9 (0x9)
[all …]
H A Dv10_structs.h29 uint32_t reserved_0; // offset: 0 (0x0)
30 uint32_t reserved_1; // offset: 1 (0x1)
31 uint32_t reserved_2; // offset: 2 (0x2)
32 uint32_t reserved_3; // offset: 3 (0x3)
33 uint32_t reserved_4; // offset: 4 (0x4)
34 uint32_t reserved_5; // offset: 5 (0x5)
35 uint32_t reserved_6; // offset: 6 (0x6)
36 uint32_t reserved_7; // offset: 7 (0x7)
37 uint32_t reserved_8; // offset: 8 (0x8)
38 uint32_t reserved_9; // offset: 9 (0x9)
[all …]
H A Dv9_structs.h28 uint32_t sdmax_rlcx_rb_cntl;
29 uint32_t sdmax_rlcx_rb_base;
30 uint32_t sdmax_rlcx_rb_base_hi;
31 uint32_t sdmax_rlcx_rb_rptr;
32 uint32_t sdmax_rlcx_rb_rptr_hi;
33 uint32_t sdmax_rlcx_rb_wptr;
34 uint32_t sdmax_rlcx_rb_wptr_hi;
35 uint32_t sdmax_rlcx_rb_wptr_poll_cntl;
36 uint32_t sdmax_rlcx_rb_rptr_addr_hi;
37 uint32_t sdmax_rlcx_rb_rptr_addr_lo;
[all …]
H A Dvi_structs.h28 uint32_t sdmax_rlcx_rb_cntl;
29 uint32_t sdmax_rlcx_rb_base;
30 uint32_t sdmax_rlcx_rb_base_hi;
31 uint32_t sdmax_rlcx_rb_rptr;
32 uint32_t sdmax_rlcx_rb_wptr;
33 uint32_t sdmax_rlcx_rb_wptr_poll_cntl;
34 uint32_t sdmax_rlcx_rb_wptr_poll_addr_hi;
35 uint32_t sdmax_rlcx_rb_wptr_poll_addr_lo;
36 uint32_t sdmax_rlcx_rb_rptr_addr_hi;
37 uint32_t sdmax_rlcx_rb_rptr_addr_lo;
[all …]
H A Dcik_structs.h28 uint32_t header;
29 uint32_t compute_dispatch_initiator;
30 uint32_t compute_dim_x;
31 uint32_t compute_dim_y;
32 uint32_t compute_dim_z;
33 uint32_t compute_start_x;
34 uint32_t compute_start_y;
35 uint32_t compute_start_z;
36 uint32_t compute_num_thread_x;
37 uint32_t compute_num_thread_y;
[all …]
H A Ddiscovery.h59 uint32_t binary_signature; /* 0x7, 0x14, 0x21, 0x28 */
76 uint32_t signature; /* Table Signature */
79 uint32_t id; /* Table ID */
107 uint32_t base_address[]; /* variable number of Addresses */
125 uint32_t base_address[]; /* Base Address list. Corresponds to the num_base_address field*/
143 …DECLARE_FLEX_ARRAY(uint32_t, base_address); /* 32-bit Base Address list. Corresponds to the num_ba…
170 uint32_t table_id; /* table ID */
173 uint32_t size; /* size of the entire header+data in bytes */
179 uint32_t gc_num_se;
180 uint32_t gc_num_wgp0_per_sa;
[all …]
H A Dkgd_kfd_interface.h51 uint32_t vmid;
52 uint32_t mc_id;
53 uint32_t status;
64 uint32_t vram_width;
65 uint32_t mem_clk_max;
106 uint32_t num_pipe_per_mec;
109 uint32_t num_queue_per_pipe;
118 uint32_t *sdma_doorbell_idx;
123 uint32_t non_cp_doorbells_start;
124 uint32_t non_cp_doorbells_en
[all...]
/openbmc/qemu/hw/net/can/
H A Dctu_can_fd_regs.h103 uint32_t u32;
107 uint32_t device_id : 16;
109 uint32_t ver_minor : 8;
110 uint32_t ver_major : 8;
112 uint32_t ver_major : 8;
113 uint32_t ver_minor : 8;
114 uint32_t device_id : 16;
124 uint32_t u32;
128 uint32_t rst : 1;
129 uint32_t lom : 1;
[all …]
/openbmc/linux/arch/mips/include/asm/octeon/
H A Dcvmx-pciercx-defs.h55 uint32_t u32;
57 __BITFIELD_FIELD(uint32_t dpe:1,
58 __BITFIELD_FIELD(uint32_t sse:1,
59 __BITFIELD_FIELD(uint32_t rma:1,
60 __BITFIELD_FIELD(uint32_t rta:1,
61 __BITFIELD_FIELD(uint32_t sta:1,
62 __BITFIELD_FIELD(uint32_t devt:2,
63 __BITFIELD_FIELD(uint32_t mdpe:1,
64 __BITFIELD_FIELD(uint32_t fbb:1,
65 __BITFIELD_FIELD(uint32_t reserved_22_22:1,
[all …]
/openbmc/qemu/include/tcg/
H A Dtcg-op-gvec-common.h25 void tcg_gen_gvec_2_ool(uint32_t dofs, uint32_t aofs,
26 uint32_t oprsz, uint32_t maxsz, int32_t data,
31 void tcg_gen_gvec_2i_ool(uint32_t dofs, uint32_t aofs, TCGv_i64 c,
32 uint32_t oprsz, uint32_t maxsz, int32_t data,
37 void tcg_gen_gvec_2_ptr(uint32_t dofs, uint32_t aofs,
38 TCGv_ptr ptr, uint32_t oprsz, uint32_t maxsz,
43 void tcg_gen_gvec_3_ool(uint32_t dofs, uint32_t aofs, uint32_t bofs,
44 uint32_t oprsz, uint32_t maxsz, int32_t data,
50 void tcg_gen_gvec_4_ool(uint32_t dofs, uint32_t aofs, uint32_t bofs,
51 uint32_t cofs, uint32_t oprsz, uint32_t maxsz,
[all …]
/openbmc/linux/drivers/gpu/drm/msm/disp/mdp5/
H A Dmdp5.xml.h191 static inline uint32_t MDSS_HW_VERSION_STEP(uint32_t val) in MDSS_HW_VERSION_STEP()
197 static inline uint32_t MDSS_HW_VERSION_MINOR(uint32_t val) in MDSS_HW_VERSION_MINOR()
203 static inline uint32_t MDSS_HW_VERSION_MAJOR(uint32_t val) in MDSS_HW_VERSION_MAJOR()
218 static inline uint32_t MDP5_HW_VERSION_STEP(uint32_t val) in MDP5_HW_VERSION_STEP()
224 static inline uint32_t MDP5_HW_VERSION_MINOR(uint32_t val) in MDP5_HW_VERSION_MINOR()
230 static inline uint32_t MDP5_HW_VERSION_MAJOR(uint32_t val) in MDP5_HW_VERSION_MAJOR()
238 static inline uint32_t MDP5_DISP_INTF_SEL_INTF0(enum mdp5_intf_type val) in MDP5_DISP_INTF_SEL_INTF0()
244 static inline uint32_t MDP5_DISP_INTF_SEL_INTF1(enum mdp5_intf_type val) in MDP5_DISP_INTF_SEL_INTF1()
250 static inline uint32_t MDP5_DISP_INTF_SEL_INTF2(enum mdp5_intf_type val) in MDP5_DISP_INTF_SEL_INTF2()
256 static inline uint32_t MDP5_DISP_INTF_SEL_INTF3(enum mdp5_intf_type val) in MDP5_DISP_INTF_SEL_INTF3()
[all …]
/openbmc/linux/drivers/gpu/drm/amd/amdkfd/
H A Dkfd_pm4_headers_ai.h32 uint32_t reserved1 : 8; /* < reserved */
33 uint32_t opcode : 8; /* < IT opcode */
34 uint32_t count : 14;/* < number of DWORDs - 1 in the
37 uint32_t type : 2; /* < packet identifier.
41 uint32_t u32All;
59 uint32_t ordinal1;
64 uint32_t vmid_mask:16;
65 uint32_t unmap_latency:8;
66 uint32_t reserved1:5;
69 uint32_t ordinal2;
[all …]
H A Dkfd_pm4_headers_vi.h32 uint32_t reserved1 : 8; /* < reserved */
33 uint32_t opcode : 8; /* < IT opcode */
34 uint32_t count : 14;/* < Number of DWORDS - 1 in the
37 uint32_t type : 2; /* < packet identifier
41 uint32_t u32All;
59 uint32_t ordinal1;
64 uint32_t vmid_mask:16;
65 uint32_t unmap_latency:8;
66 uint32_t reserved1:5;
69 uint32_t ordinal2;
[all …]
/openbmc/linux/drivers/scsi/arcmsr/
H A Darcmsr.h104 #define dma_addr_hi32(addr) (uint32_t) ((addr>>16)>>16)
105 #define dma_addr_lo32(addr) (uint32_t) (addr & 0xffffffff)
113 uint32_t HeaderLength;
115 uint32_t Timeout;
116 uint32_t ControlCode;
117 uint32_t ReturnCode;
118 uint32_t Length;
196 uint32_t data_len;
206 uint32_t signature; /*0, 00-03*/
207 uint32_t request_len; /*1, 04-07*/
[all …]
/openbmc/linux/sound/soc/qcom/qdsp6/
H A Daudioreach.h68 uint32_t property_flag;
72 uint32_t shm_addr_lsw;
73 uint32_t shm_addr_msw;
74 uint32_t mem_size_bytes;
78 uint32_t mem_map_handle;
82 uint32_t mem_map_handle;
91 uint32_t num_modules_list;
97 uint32_t num_modules_prop_cfg;
101 uint32_t instance_id;
102 uint32_t num_props;
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/include/
H A Dgrph_object_ctrl_defs.h67 uint32_t enum_id:16; /* 1 based enum */
73 uint32_t clk_mask_register_index;
74 uint32_t clk_en_register_index;
75 uint32_t clk_y_register_index;
76 uint32_t clk_a_register_index;
77 uint32_t data_mask_register_index;
78 uint32_t data_en_register_index;
79 uint32_t data_y_register_index;
80 uint32_t data_a_register_index;
82 uint32_t clk_mask_shift;
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-mxs/
H A Dregs-digctl.h21 uint32_t hw_digctl_writeonce; /* 0x060 */
22 uint32_t reserved_writeonce[3];
25 uint32_t hw_digctl_entropy; /* 0x090 */
26 uint32_t reserved_entropy[3];
27 uint32_t hw_digctl_entropy_latched; /* 0x0a0 */
28 uint32_t reserved_entropy_latched[3];
30 uint32_t reserved1[4];
33 uint32_t hw_digctl_dbgrd; /* 0x0d0 */
34 uint32_t reserved_hw_digctl_dbgrd[3];
35 uint32_t hw_digctl_dbg; /* 0x0e0 */
[all …]
/openbmc/linux/tools/firewire/
H A Dnosy-dump.h15 uint32_t timestamp;
18 uint32_t zero:24;
19 uint32_t phy_id:6;
20 uint32_t identifier:2;
24 uint32_t zero:16;
25 uint32_t gap_count:6;
26 uint32_t set_gap_count:1;
27 uint32_t set_root:1;
28 uint32_t root_id:6;
29 uint32_t identifier:2;
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-ep93xx/
H A Dep93xx.h35 uint32_t control;
36 uint32_t interrupt;
37 uint32_t ppalloc;
38 uint32_t status;
39 uint32_t reserved0;
40 uint32_t remain;
41 uint32_t reserved1[2];
42 uint32_t maxcnt0;
43 uint32_t base0;
44 uint32_t current0;
[all …]
/openbmc/linux/drivers/gpu/drm/msm/adreno/
H A Da6xx.xml.h1123 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_MRB_START(uint32_t val) in A6XX_CP_ROQ_THRESHOLDS_1_MRB_START()
1129 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_VSD_START(uint32_t val) in A6XX_CP_ROQ_THRESHOLDS_1_VSD_START()
1135 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_IB1_START(uint32_t val) in A6XX_CP_ROQ_THRESHOLDS_1_IB1_START()
1141 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_IB2_START(uint32_t val) in A6XX_CP_ROQ_THRESHOLDS_1_IB2_START()
1149 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_2_SDS_START(uint32_t val) in A6XX_CP_ROQ_THRESHOLDS_2_SDS_START()
1155 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE(uint32_t val) in A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE()
1173 static inline uint32_t REG_A6XX_CP_SCRATCH(uint32_t i0) { return 0x00000883 + 0x1*i0; } in REG_A6XX_CP_SCRATCH()
1175 static inline uint32_t REG_A6XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000883 + 0x1*i0; } in REG_A6XX_CP_SCRATCH_REG()
1177 static inline uint32_t REG_A6XX_CP_PROTECT(uint32_t i0) { return 0x00000850 + 0x1*i0; } in REG_A6XX_CP_PROTECT()
1179 static inline uint32_t REG_A6XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000850 + 0x1*i0; } in REG_A6XX_CP_PROTECT_REG()
[all …]
/openbmc/u-boot/include/
H A Dimx_lpi2c.h94 #define LPI2C_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_FEATUR…
97 #define LPI2C_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MINOR_…
100 #define LPI2C_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MAJOR_…
105 #define LPI2C_PARAM_MTXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MTXFIF…
108 #define LPI2C_PARAM_MRXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MRXFIF…
113 #define LPI2C_MCR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_MEN_SHIF…
116 #define LPI2C_MCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RST_SHIF…
119 #define LPI2C_MCR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DOZEN_SH…
122 #define LPI2C_MCR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DBGEN_SH…
125 #define LPI2C_MCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RTF_SHIF…
[all …]
/openbmc/linux/drivers/gpu/drm/msm/disp/mdp4/
H A Dmdp4.xml.h120 static inline uint32_t MDP4_VERSION_MINOR(uint32_t val) in MDP4_VERSION_MINOR()
126 static inline uint32_t MDP4_VERSION_MAJOR(uint32_t val) in MDP4_VERSION_MAJOR()
148 static inline uint32_t MDP4_DISP_INTF_SEL_PRIM(enum mdp4_intf val) in MDP4_DISP_INTF_SEL_PRIM()
154 static inline uint32_t MDP4_DISP_INTF_SEL_SEC(enum mdp4_intf val) in MDP4_DISP_INTF_SEL_SEC()
160 static inline uint32_t MDP4_DISP_INTF_SEL_EXT(enum mdp4_intf val) in MDP4_DISP_INTF_SEL_EXT()
190 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE0(enum mdp_mixer_stage_id val) in MDP4_LAYERMIXER2_IN_CFG_PIPE0()
197 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE1(enum mdp_mixer_stage_id val) in MDP4_LAYERMIXER2_IN_CFG_PIPE1()
204 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE2(enum mdp_mixer_stage_id val) in MDP4_LAYERMIXER2_IN_CFG_PIPE2()
211 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE3(enum mdp_mixer_stage_id val) in MDP4_LAYERMIXER2_IN_CFG_PIPE3()
218 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE4(enum mdp_mixer_stage_id val) in MDP4_LAYERMIXER2_IN_CFG_PIPE4()
[all …]
/openbmc/linux/drivers/gpu/drm/meson/
H A Dmeson_drv.h70 uint32_t osd1_ctrl_stat;
71 uint32_t osd1_ctrl_stat2;
72 uint32_t osd1_blk0_cfg[5];
73 uint32_t osd1_blk1_cfg4;
74 uint32_t osd1_blk2_cfg4;
75 uint32_t osd1_addr;
76 uint32_t osd1_stride;
77 uint32_t osd1_height;
78 uint32_t osd1_width;
79 uint32_t osd_sc_ctrl0;
[all …]
/openbmc/u-boot/drivers/net/
H A Dfec_mxc.h26 uint32_t res0[1]; /* MBAR_ETH + 0x000 */
27 uint32_t ievent; /* MBAR_ETH + 0x004 */
28 uint32_t imask; /* MBAR_ETH + 0x008 */
30 uint32_t res1[1]; /* MBAR_ETH + 0x00C */
31 uint32_t r_des_active; /* MBAR_ETH + 0x010 */
32 uint32_t x_des_active; /* MBAR_ETH + 0x014 */
33 uint32_t res2[3]; /* MBAR_ETH + 0x018-20 */
34 uint32_t ecntrl; /* MBAR_ETH + 0x024 */
36 uint32_t res3[6]; /* MBAR_ETH + 0x028-03C */
37 uint32_t mii_data; /* MBAR_ETH + 0x040 */
[all …]
/openbmc/linux/drivers/scsi/lpfc/
H A Dlpfc_hw.h80 uint32_t Revision:8;
81 uint32_t InId:24;
83 uint32_t word;
92 uint32_t word;
155 uint32_t PortId; /* For RNN_ID requests */
164 uint32_t port_id;
167 uint32_t PortId;
172 uint32_t PortId;
178 uint32_t PortId;
181 uint32_t fc4_types[8];
[all …]

12345678910>>...161