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Searched refs:topckgen (Results 1 – 25 of 54) sorted by relevance

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/openbmc/linux/Documentation/devicetree/bindings/sound/
H A Dmt2701-afe-pcm.txt69 <&topckgen CLK_TOP_AUD_MUX1_SEL>,
70 <&topckgen CLK_TOP_AUD_MUX2_SEL>,
71 <&topckgen CLK_TOP_AUD_48K_TIMING>,
72 <&topckgen CLK_TOP_AUD_44K_TIMING>,
73 <&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
74 <&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
75 <&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
76 <&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
77 <&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
78 <&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
[all …]
H A Dmtk-afe-pcm.txt26 <&topckgen TOP_AUDIO_SEL>,
27 <&topckgen TOP_AUD_INTBUS_SEL>,
28 <&topckgen TOP_APLL1_DIV0>,
29 <&topckgen TOP_APLL2_DIV0>,
30 <&topckgen TOP_I2S0_M_CK_SEL>,
31 <&topckgen TOP_I2S1_M_CK_SEL>,
32 <&topckgen TOP_I2S2_M_CK_SEL>,
33 <&topckgen TOP_I2S3_M_CK_SEL>,
34 <&topckgen TOP_I2S3_B_CK_SEL>;
H A Dmt6797-afe-pcm.txt29 <&topckgen CLK_TOP_MUX_AUDIO>,
30 <&topckgen CLK_TOP_MUX_AUD_INTBUS>,
31 <&topckgen CLK_TOP_SYSPLL3_D4>,
32 <&topckgen CLK_TOP_SYSPLL1_D4>,
H A Dmt8183-afe-pcm.txt32 <&topckgen CLK_TOP_MUX_AUDIO>,
33 <&topckgen CLK_TOP_MUX_AUD_INTBUS>,
34 <&topckgen CLK_TOP_SYSPLL_D2_D4>,
/openbmc/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8516.dtsi58 <&topckgen CLK_TOP_MAINPLL_D2>;
71 <&topckgen CLK_TOP_MAINPLL_D2>;
84 <&topckgen CLK_TOP_MAINPLL_D2>;
97 <&topckgen CLK_TOP_MAINPLL_D2>;
182 topckgen: topckgen@10000000 { label
183 compatible = "mediatek,mt8516-topckgen", "syscon";
218 clocks = <&topckgen CLK_TOP_CLK26M_D2>,
219 <&topckgen CLK_TOP_APXGPT>;
251 clocks = <&topckgen CLK_TOP_PMICWRAP_26M>,
252 <&topckgen CLK_TOP_PMICWRAP_AP>;
[all …]
H A Dmt8192.dtsi443 topckgen: syscon@10000000 { label
444 compatible = "mediatek,mt8192-topckgen", "syscon";
501 clocks = <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
519 clocks = <&topckgen CLK_TOP_MFG_PLL_SEL>,
520 <&topckgen CLK_TOP_MFG_REF_SEL>;
562 clocks = <&topckgen CLK_TOP_DISP_SEL>,
576 clocks = <&topckgen CLK_TOP_IPE_SEL>,
589 clocks = <&topckgen CLK_TOP_IMG1_SEL>,
599 clocks = <&topckgen CLK_TOP_IMG2_SEL>,
609 clocks = <&topckgen CLK_TOP_MDP_SEL>,
[all …]
H A Dmt7622.dtsi251 clocks = <&topckgen CLK_TOP_HIF_SEL>;
260 <&topckgen CLK_TOP_AXI_SEL>;
292 topckgen: clock-controller@10210000 { label
293 compatible = "mediatek,mt7622-topckgen";
331 clocks = <&topckgen CLK_TOP_RTC>;
395 clocks = <&topckgen CLK_TOP_UART_SEL>,
406 clocks = <&topckgen CLK_TOP_UART_SEL>,
417 clocks = <&topckgen CLK_TOP_UART_SEL>,
428 clocks = <&topckgen CLK_TOP_UART_SEL>,
439 clocks = <&topckgen CLK_TOP_PWM_SEL>,
[all …]
H A Dmt7986a.dtsi156 topckgen: topckgen@1001b000 { label
157 compatible = "mediatek,mt7986-topckgen", "syscon";
202 clocks = <&topckgen CLK_TOP_PWM_SEL>,
242 assigned-clocks = <&topckgen CLK_TOP_EIP_B_SEL>;
255 assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
257 assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
258 <&topckgen CLK_TOP_UART_SEL>;
271 assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>;
284 assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>;
308 clocks = <&topckgen CLK_TOP_MPLL_D2>,
[all …]
H A Dmt2712e.dtsi90 <&topckgen CLK_TOP_F_MP0_PLL1>;
103 <&topckgen CLK_TOP_F_MP0_PLL1>;
116 <&topckgen CLK_TOP_F_BIG_PLL1>;
246 topckgen: syscon@10000000 { label
247 compatible = "mediatek,mt2712-topckgen", "syscon";
285 clocks = <&topckgen CLK_TOP_MM_SEL>,
286 <&topckgen CLK_TOP_MFG_SEL>,
287 <&topckgen CLK_TOP_VENC_SEL>,
288 <&topckgen CLK_TOP_JPGDEC_SEL>,
289 <&topckgen CLK_TOP_A1SYS_HP_SEL>,
[all …]
H A Dmt8186.dtsi846 topckgen: syscon@10000000 { label
847 compatible = "mediatek,mt8186-topckgen", "syscon";
898 clocks = <&topckgen CLK_TOP_MFG>;
925 clocks = <&topckgen CLK_TOP_SENINF>,
926 <&topckgen CLK_TOP_SENINF1>;
934 clocks = <&topckgen CLK_TOP_USB_TOP>,
950 clocks = <&topckgen CLK_TOP_AUDIODSP>,
951 <&topckgen CLK_TOP_ADSP_BUS>;
980 clocks = <&topckgen CLK_TOP_DISP>,
981 <&topckgen CLK_TOP_MDP>,
[all …]
H A Dmt8195.dtsi483 topckgen: syscon@10000000 { label
484 compatible = "mediatek,mt8195-topckgen", "syscon";
544 <&topckgen CLK_TOP_MFG_CORE_TMP>;
580 clocks = <&topckgen CLK_TOP_VPP>,
581 <&topckgen CLK_TOP_CAM>,
582 <&topckgen CLK_TOP_CCU>,
583 <&topckgen CLK_TOP_IMG>,
584 <&topckgen CLK_TOP_VENC>,
585 <&topckgen CLK_TOP_VDEC>,
586 <&topckgen CLK_TOP_WPE_VPP>,
[all …]
H A Dmt8173.dtsi349 topckgen: clock-controller@10000000 { label
350 compatible = "mediatek,mt8173-topckgen";
459 clocks = <&topckgen CLK_TOP_MM_SEL>;
465 clocks = <&topckgen CLK_TOP_MM_SEL>,
466 <&topckgen CLK_TOP_VENC_SEL>;
472 clocks = <&topckgen CLK_TOP_MM_SEL>;
478 clocks = <&topckgen CLK_TOP_MM_SEL>;
485 clocks = <&topckgen CLK_TOP_MM_SEL>,
486 <&topckgen CLK_TOP_VENC_LT_SEL>;
534 <&topckgen CLK_TOP_RTC_SEL>;
[all …]
H A Dmt8167.dtsi20 topckgen: topckgen@10000000 { label
21 compatible = "mediatek,mt8167-topckgen", "syscon";
51 clocks = <&topckgen CLK_TOP_SMI_MM>;
59 clocks = <&topckgen CLK_TOP_SMI_MM>,
60 <&topckgen CLK_TOP_RG_VDEC>;
67 clocks = <&topckgen CLK_TOP_SMI_MM>;
74 clocks = <&topckgen CLK_TOP_RG_AXI_MFG>,
75 <&topckgen CLK_TOP_RG_SLOW_MFG>;
H A Dmt8183.dtsi286 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
335 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
358 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
381 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
404 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
427 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
450 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
473 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
496 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
803 topckgen: syscon@10000000 { label
[all …]
H A Dmt6795.dtsi250 topckgen: syscon@10000000 { label
251 compatible = "mediatek,mt6795-topckgen", "syscon";
285 clocks = <&topckgen CLK_TOP_MM_SEL>;
291 clocks = <&topckgen CLK_TOP_MM_SEL>,
292 <&topckgen CLK_TOP_VENC_SEL>;
298 clocks = <&topckgen CLK_TOP_MM_SEL>;
305 clocks = <&topckgen CLK_TOP_MM_SEL>;
313 clocks = <&topckgen CLK_TOP_MM_SEL>,
314 <&topckgen CLK_TOP_MJC_SEL>;
384 clocks = <&topckgen CLK_TOP_PMICSPI_SEL>, <&clk26m>;
[all …]
H A Dmt8365.dtsi278 topckgen: syscon@10000000 { label
279 compatible = "mediatek,mt8365-topckgen", "syscon";
482 clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>,
483 <&topckgen CLK_TOP_SPI_SEL>,
508 clocks = <&topckgen CLK_TOP_SSUSB_TOP_CK_EN>,
523 clocks = <&topckgen CLK_TOP_SSUSB_TOP_CK_EN>,
539 clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>,
551 clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>,
563 clocks = <&topckgen CLK_TOP_MSDC50_2_SEL>,
578 clocks = <&topckgen CLK_TOP_ETH_SEL>,
[all …]
H A Dmt6797.dtsi114 topckgen: topckgen@10000000 { label
115 compatible = "mediatek,mt6797-topckgen";
213 clocks = <&topckgen CLK_TOP_MUX_MFG>,
214 <&topckgen CLK_TOP_MUX_MM>,
215 <&topckgen CLK_TOP_MUX_VDEC>;
/openbmc/u-boot/arch/arm/dts/
H A Dmt7629.dtsi85 clocks = <&topckgen CLK_TOP_10M_SEL>,
86 <&topckgen CLK_TOP_CLKXTAL_D4>;
94 clocks = <&topckgen CLK_TOP_HIF_SEL>;
96 assigned-clocks = <&topckgen CLK_TOP_HIF_SEL>;
97 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>;
122 clocks = <&topckgen CLK_TOP_DDRPHYCFG_SEL>,
123 <&topckgen CLK_TOP_SYSPLL1_D8>,
124 <&topckgen CLK_TOP_MEM_SEL>,
125 <&topckgen CLK_TOP_DMPLL>;
137 topckgen: clock-controller@10210000 { label
[all …]
H A Dmt7623.dtsi99 topckgen: clock-controller@10000000 { label
100 compatible = "mediatek,mt7623-topckgen";
135 clocks = <&topckgen CLK_TOP_MM_SEL>,
136 <&topckgen CLK_TOP_MFG_SEL>,
137 <&topckgen CLK_TOP_ETHIF_SEL>;
191 clocks = <&topckgen CLK_TOP_UART_SEL>,
202 clocks = <&topckgen CLK_TOP_UART_SEL>,
213 clocks = <&topckgen CLK_TOP_UART_SEL>,
225 clocks = <&topckgen CLK_TOP_UART_SEL>,
236 <&topckgen CLK_TOP_MSDC30_0_SEL>;
[all …]
/openbmc/linux/arch/arm/boot/dts/mediatek/
H A Dmt7629.dtsi98 clocks = <&topckgen CLK_TOP_HIF_SEL>;
100 assigned-clocks = <&topckgen CLK_TOP_HIF_SEL>;
101 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>;
137 topckgen: syscon@10210000 { label
138 compatible = "mediatek,mt7629-topckgen", "syscon";
215 clocks = <&topckgen CLK_TOP_UART_SEL>,
226 clocks = <&topckgen CLK_TOP_UART_SEL>,
237 clocks = <&topckgen CLK_TOP_UART_SEL>,
247 clocks = <&topckgen CLK_TOP_PWM_SEL>,
251 assigned-clocks = <&topckgen CLK_TOP_PWM_SEL>;
[all …]
H A Dmt2701.dtsi126 topckgen: syscon@10000000 { label
127 compatible = "mediatek,mt2701-topckgen", "syscon";
156 clocks = <&topckgen CLK_TOP_MM_SEL>,
157 <&topckgen CLK_TOP_MFG_SEL>,
158 <&topckgen CLK_TOP_ETHIF_SEL>;
342 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
343 <&topckgen CLK_TOP_SPI0_SEL>,
389 <&topckgen CLK_TOP_FLASH_SEL>;
402 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
403 <&topckgen CLK_TOP_SPI1_SEL>,
[all …]
H A Dmt7623.dtsi226 topckgen: syscon@10000000 { label
227 compatible = "mediatek,mt7623-topckgen",
228 "mediatek,mt2701-topckgen",
277 clocks = <&topckgen CLK_TOP_MM_SEL>,
278 <&topckgen CLK_TOP_MFG_SEL>,
279 <&topckgen CLK_TOP_ETHIF_SEL>;
423 clocks = <&topckgen CLK_TOP_PWM_SEL>,
487 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
488 <&topckgen CLK_TOP_SPI0_SEL>,
552 <&topckgen CLK_TOP_FLASH_SEL>;
[all …]
H A Dmt8135.dtsi127 topckgen: topckgen@10000000 { label
128 compatible = "mediatek,mt8135-topckgen";
/openbmc/linux/drivers/clk/mediatek/
H A DMakefile22 clk-mt6795-pericfg.o clk-mt6795-topckgen.o
58 obj-$(CONFIG_COMMON_CLK_MT7981) += clk-mt7981-topckgen.o
62 obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-topckgen.o
73 clk-mt8173-pericfg.o clk-mt8173-topckgen.o
90 obj-$(CONFIG_COMMON_CLK_MT8186) += clk-mt8186-apmixedsys.o clk-mt8186-topckgen.o \
103 obj-$(CONFIG_COMMON_CLK_MT8188) += clk-mt8188-apmixedsys.o clk-mt8188-topckgen.o \
129 obj-$(CONFIG_COMMON_CLK_MT8195) += clk-mt8195-apmixedsys.o clk-mt8195-topckgen.o \
/openbmc/linux/Documentation/devicetree/bindings/soc/mediatek/
H A Dscpsys.txt67 <&topckgen CLK_TOP_MM_SEL>;
68 <&topckgen CLK_TOP_VENC_SEL>,
69 <&topckgen CLK_TOP_VENC_LT_SEL>;

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