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Searched refs:tg_mask (Results 1 – 25 of 26) sorted by relevance

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/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn301/
H A Ddcn301_optc.c43 optc1->tg_shift->field_name, optc1->tg_mask->field_name
177 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1; in dcn301_timing_generator_init()
178 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1; in dcn301_timing_generator_init()
H A Ddcn301_resource.c856 tgn10->tg_mask = &optc_mask; in dcn301_timing_generator_create()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn201/
H A Ddcn201_optc.c39 optc1->tg_shift->field_name, optc1->tg_mask->field_name
194 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1; in dcn201_timing_generator_init()
195 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1; in dcn201_timing_generator_init()
H A Ddcn201_resource.c513 static const struct dcn_optc_mask tg_mask = { variable
770 tgn10->tg_mask = &tg_mask; in dcn201_timing_generator_create()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn314/
H A Ddcn314_optc.c43 optc1->tg_shift->field_name, optc1->tg_mask->field_name
264 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1; in dcn314_timing_generator_init()
265 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1; in dcn314_timing_generator_init()
H A Ddcn314_resource.c1140 tgn10->tg_mask = &optc_mask; in dcn31_timing_generator_create()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn31/
H A Ddcn31_optc.c41 optc1->tg_shift->field_name, optc1->tg_mask->field_name
301 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1; in dcn31_timing_generator_init()
302 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1; in dcn31_timing_generator_init()
H A Ddcn31_resource.c1068 tgn10->tg_mask = &optc_mask; in dcn31_timing_generator_create()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn32/
H A Ddcn32_optc.c43 optc1->tg_shift->field_name, optc1->tg_mask->field_name
337 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1; in dcn32_timing_generator_init()
338 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1; in dcn32_timing_generator_init()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_optc.c43 optc1->tg_shift->field_name, optc1->tg_mask->field_name
385 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1; in dcn30_timing_generator_init()
386 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1; in dcn30_timing_generator_init()
H A Ddcn30_resource.c901 tgn10->tg_mask = &optc_mask; in dcn30_timing_generator_create()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_optc.c38 optc1->tg_shift->field_name, optc1->tg_mask->field_name
579 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1; in dcn20_timing_generator_init()
580 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1; in dcn20_timing_generator_init()
H A Ddcn20_resource.c518 static const struct dcn_optc_mask tg_mask = { variable
898 tgn10->tg_mask = &tg_mask; in dcn20_timing_generator_create()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_optc.c40 optc1->tg_shift->field_name, optc1->tg_mask->field_name
303 if (REG(OPTC_DATA_FORMAT_CONTROL) && optc1->tg_mask->OPTC_DATA_FORMAT != 0) { in optc1_program_timing()
314 if (optc1->tg_mask->OTG_H_TIMING_DIV_MODE != 0) { in optc1_program_timing()
1591 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1; in dcn10_timing_generator_init()
1592 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1; in dcn10_timing_generator_init()
H A Ddcn10_resource.c402 static const struct dcn_optc_mask tg_mask = { variable
723 tgn10->tg_mask = &tg_mask; in dcn10_timing_generator_create()
H A Ddcn10_optc.h572 const struct dcn_optc_mask *tg_mask; member
/openbmc/linux/drivers/net/ethernet/mscc/
H A Docelot_vcap.c46 u32 tg_mask; /* Current type-group mask */ member
199 data->tg_mask = 0; in vcap_data_offset_get()
203 data->tg_mask |= GENMASK(offset + width - 1, offset); in vcap_data_offset_get()
365 data.tg = (data.tg & ~data.tg_mask); in is2_entry_set()
688 data.tg = (data.tg & ~data.tg_mask); in is1_entry_set()
826 data.tg = (data.tg & ~data.tg_mask); in es0_entry_set()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/
H A Ddcn32_clk_mgr.c250 uint32_t tg_mask = 0; in dcn32_update_clocks_update_dtb_dto() local
259 !(tg_mask & (1 << pipe_ctx->stream_res.tg->inst))) { in dcn32_update_clocks_update_dtb_dto()
260 tg_mask |= (1 << pipe_ctx->stream_res.tg->inst); in dcn32_update_clocks_update_dtb_dto()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn21/
H A Ddcn21_resource.c272 static const struct dcn_optc_mask tg_mask = { variable
1074 tgn10->tg_mask = &tg_mask; in dcn21_timing_generator_create()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dml/dcn30/
H A Ddcn30_fpu.c44 optc1->tg_shift->field_name, optc1->tg_mask->field_name
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn302/
H A Ddcn302_resource.c613 tgn10->tg_mask = &optc_mask; in dcn302_timing_generator_create()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn303/
H A Ddcn303_resource.c567 tgn10->tg_mask = &optc_mask; in dcn303_timing_generator_create()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn316/
H A Ddcn316_resource.c1062 tgn10->tg_mask = &optc_mask; in dcn31_timing_generator_create()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn315/
H A Ddcn315_resource.c1066 tgn10->tg_mask = &optc_mask; in dcn31_timing_generator_create()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn321/
H A Ddcn321_resource.c1009 tgn10->tg_mask = &optc_mask; in dcn321_timing_generator_create()

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