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Searched refs:tcg_target_available_regs (Results 1 – 11 of 11) sorted by relevance

/openbmc/qemu/tcg/riscv/
H A Dtcg-target.c.inc2899 tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff;
2900 tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff;
2928 tcg_target_available_regs[TCG_TYPE_V64] = ALL_VECTOR_REGS;
2929 tcg_target_available_regs[TCG_TYPE_V128] = ALL_DVECTOR_REG_GROUPS;
2930 tcg_target_available_regs[TCG_TYPE_V256] = ALL_QVECTOR_REG_GROUPS;
2934 tcg_target_available_regs[TCG_TYPE_V64] = ALL_VECTOR_REGS;
2935 tcg_target_available_regs[TCG_TYPE_V128] = ALL_VECTOR_REGS;
2936 tcg_target_available_regs[TCG_TYPE_V256] = ALL_DVECTOR_REG_GROUPS;
2942 tcg_target_available_regs[TCG_TYPE_V64] = ALL_VECTOR_REGS;
2943 tcg_target_available_regs[TCG_TYPE_V128] = ALL_VECTOR_REGS;
[all …]
/openbmc/qemu/tcg/
H A Dtcg.c252 static TCGRegSet tcg_target_available_regs[TCG_TYPE_COUNT]; variable
3398 = (ts->state == TS_DEAD ? 0 : tcg_target_available_regs[ts->type]); in la_reset_pref()
3517 set = tcg_target_available_regs[ts->type] & mask; in la_cross_call()
3703 tcg_target_available_regs[ts->type]; in liveness_pass_1()
3891 *la_temp_pref(ts) = tcg_target_available_regs[ts->type]; in liveness_pass_1()
4277 temp_load(s, ts, tcg_target_available_regs[ts->type], in temp_sync()
4629 temp_load(s, ts, tcg_target_available_regs[itype], in tcg_reg_alloc_mov()
4663 oreg = tcg_reg_alloc(s, tcg_target_available_regs[otype], in tcg_reg_alloc_mov()
4916 temp_load(s, ts, tcg_target_available_regs[ts->type], in tcg_reg_alloc_op()
5012 nr = tcg_reg_alloc(s, tcg_target_available_regs[ts->type], in tcg_reg_alloc_op()
[all …]
/openbmc/qemu/tcg/loongarch64/
H A Dtcg-target.c.inc2469 tcg_target_available_regs[TCG_TYPE_I32] = ALL_GENERAL_REGS;
2470 tcg_target_available_regs[TCG_TYPE_I64] = ALL_GENERAL_REGS;
2485 tcg_target_available_regs[TCG_TYPE_V64] = ALL_VECTOR_REGS;
2486 tcg_target_available_regs[TCG_TYPE_V128] = ALL_VECTOR_REGS;
2488 tcg_target_available_regs[TCG_TYPE_V256] = ALL_VECTOR_REGS;
/openbmc/qemu/tcg/tci/
H A Dtcg-target.c.inc933 tcg_target_available_regs[TCG_TYPE_I32] = BIT(TCG_TARGET_NB_REGS) - 1;
935 tcg_target_available_regs[TCG_TYPE_I64] = BIT(TCG_TARGET_NB_REGS) - 1;
/openbmc/qemu/tcg/aarch64/
H A Dtcg-target.c.inc3156 tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffffu;
3157 tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffffu;
3158 tcg_target_available_regs[TCG_TYPE_V64] = 0xffffffff00000000ull;
3159 tcg_target_available_regs[TCG_TYPE_V128] = 0xffffffff00000000ull;
/openbmc/qemu/tcg/sparc64/
H A Dtcg-target.c.inc1640 tcg_target_available_regs[TCG_TYPE_I32] = ALL_GENERAL_REGS;
1641 tcg_target_available_regs[TCG_TYPE_I64] = ALL_GENERAL_REGS;
/openbmc/qemu/tcg/s390x/
H A Dtcg-target.c.inc3499 tcg_target_available_regs[TCG_TYPE_I32] = 0xffff;
3500 tcg_target_available_regs[TCG_TYPE_I64] = 0xffff;
3502 tcg_target_available_regs[TCG_TYPE_V64] = 0xffffffff00000000ull;
3503 tcg_target_available_regs[TCG_TYPE_V128] = 0xffffffff00000000ull;
/openbmc/qemu/tcg/i386/
H A Dtcg-target.c.inc4424 tcg_target_available_regs[TCG_TYPE_I32] = ALL_GENERAL_REGS;
4426 tcg_target_available_regs[TCG_TYPE_I64] = ALL_GENERAL_REGS;
4429 tcg_target_available_regs[TCG_TYPE_V64] = ALL_VECTOR_REGS;
4430 tcg_target_available_regs[TCG_TYPE_V128] = ALL_VECTOR_REGS;
4433 tcg_target_available_regs[TCG_TYPE_V256] = ALL_VECTOR_REGS;
/openbmc/qemu/tcg/arm/
H A Dtcg-target.c.inc2291 tcg_target_available_regs[TCG_TYPE_I32] = ALL_GENERAL_REGS;
2302 tcg_target_available_regs[TCG_TYPE_V64] = ALL_VECTOR_REGS;
2303 tcg_target_available_regs[TCG_TYPE_V128] = ALL_VECTOR_REGS;
/openbmc/qemu/tcg/ppc/
H A Dtcg-target.c.inc4365 tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff;
4366 tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff;
4368 tcg_target_available_regs[TCG_TYPE_V64] = 0xffffffff00000000ull;
4369 tcg_target_available_regs[TCG_TYPE_V128] = 0xffffffff00000000ull;
/openbmc/qemu/tcg/mips/
H A Dtcg-target.c.inc2586 tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff;
2588 tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff;