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Searched refs:tWTR (Results 1 – 17 of 17) sorted by relevance

/openbmc/linux/drivers/memory/
H A Djedec_ddr_data.c42 .tWTR = 10000,
63 .tWTR = 7500,
84 .tWTR = 7500,
105 .tWTR = 7500,
126 .tWTR = 2,
H A Djedec_ddr.h155 u32 tWTR; member
179 u32 tWTR; member
235 u32 tWTR; member
264 u32 tWTR; member
H A Dof_memory.c43 ret |= of_property_read_u32(np, "tWTR-min-tck", &min->tWTR); in of_get_min_tck()
75 ret |= of_property_read_u32(np, "tWTR", &tim->tWTR); in of_do_get_timings()
182 ret |= of_property_read_u32(np, "tWTR-min-tck", &min->tWTR); in of_lpddr3_get_min_tck()
228 ret |= of_property_read_u32(np, "tWTR", &tim->tWTR); in of_lpddr3_do_get_timings()
/openbmc/linux/arch/arm/boot/dts/ti/omap/
H A Delpida_ecb240abacn.dtsi17 tWTR-min-tck = <2>;
33 tWTR = <7500>;
55 tWTR = <10000>;
/openbmc/u-boot/arch/arm/mach-sunxi/
H A Ddram_sun9i.c122 struct dram_sun9i_timing tWTR; member
385 const u32 tWTR = MAX(para->tWTR.ck, PS2CYCLES_ROUNDUP(para->tWTR.ps)); in mctl_channel_init() local
518 #define WR2PRE (MCTL_BL/2 + CWL + tWTR) in mctl_channel_init()
520 #define WR2RD (MCTL_BL/2 + CWL + tWTR) in mctl_channel_init()
642 (tRCD << 12) | (tRP << 8) | (tWTR << 4) | (tRTP << 0), in mctl_channel_init()
895 .tWTR = { .ck = 4, .ps = 7500 }, in sunxi_dram_init()
/openbmc/u-boot/arch/arm/mach-omap2/omap5/
H A Demif.c61 .tWTR = 2,
H A Dsdram.c642 .tWTR = 2,
/openbmc/u-boot/arch/arm/mach-omap2/omap4/
H A Demif.c84 .tWTR = 2,
H A Dsdram_elpida.c266 .tWTR = 2,
/openbmc/u-boot/board/tbs/tbs2910/
H A Dtbs2910.cfg83 /* tDLLK=0x1ff+1,tRTP=3+1,tWTR=3+1,tRRD=3+1 */
/openbmc/linux/drivers/memory/samsung/
H A Dexynos5422-dmc.c1087 val = dmc->timings->tWTR / clk_period_ps; in create_timings_aligned()
1088 val += dmc->timings->tWTR % clk_period_ps ? 1 : 0; in create_timings_aligned()
1089 val = max(val, dmc->min_tck->tWTR); in create_timings_aligned()
/openbmc/linux/arch/arm/boot/dts/samsung/
H A Dexynos5422-odroid-core.dtsi348 tWTR-min-tck = <2>;
374 tWTR = <3750>;
/openbmc/u-boot/board/buffalo/lsxl/
H A Dkwbimage-lschl.cfg59 # bit19-16: 2, 3 cyle tWTR
H A Dkwbimage-lsxhl.cfg59 # bit19-16: 2, 3 cyle tWTR
/openbmc/u-boot/board/d-link/dns325/
H A Dkwbimage.cfg56 # bit19-16: 2, 3 cyle tWTR
/openbmc/u-boot/arch/arm/include/asm/
H A Demif.h1176 u32 tWTR; member
/openbmc/u-boot/arch/arm/mach-omap2/
H A Demif-common.c687 val = max(min_tck->tWTR, ns_x2_2_cycles(timings->tWTRx2)) - 1; in get_sdram_tim_1_reg()