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Searched refs:tWR (Results 1 – 18 of 18) sorted by relevance

/openbmc/linux/drivers/memory/
H A Djedec_ddr_data.c39 .tWR = 15000,
60 .tWR = 15000,
81 .tWR = 15000,
102 .tWR = 15000,
123 .tWR = 3,
H A Djedec_ddr.h152 u32 tWR; member
176 u32 tWR; member
236 u32 tWR; member
265 u32 tWR; member
H A Dof_memory.c40 ret |= of_property_read_u32(np, "tWR-min-tck", &min->tWR); in of_get_min_tck()
72 ret |= of_property_read_u32(np, "tWR", &tim->tWR); in of_do_get_timings()
183 ret |= of_property_read_u32(np, "tWR-min-tck", &min->tWR); in of_lpddr3_get_min_tck()
229 ret |= of_property_read_u32(np, "tWR", &tim->tWR); in of_lpddr3_do_get_timings()
/openbmc/u-boot/arch/arm/mach-omap2/omap4/
H A Demif.c28 .tWR = 15,
52 .tWR = 15,
81 .tWR = 3,
H A Dsdram_elpida.c195 .tWR = 15,
218 .tWR = 15,
241 .tWR = 15,
263 .tWR = 3,
/openbmc/linux/arch/arm/boot/dts/ti/omap/
H A Delpida_ecb240abacn.dtsi14 tWR-min-tck = <3>;
30 tWR = <15000>;
52 tWR = <15000>;
/openbmc/u-boot/arch/arm/mach-omap2/omap5/
H A Demif.c29 .tWR = 15,
58 .tWR = 3,
H A Dsdram.c617 .tWR = 15,
639 .tWR = 3,
/openbmc/u-boot/arch/arm/mach-sunxi/
H A Ddram_sun9i.c123 u32 tWR; /* in nCK */ member
386 const u32 tWR = NS2CYCLES_FLOOR(para->tWR); in mctl_channel_init() local
460 mr[0] = DDR3_MR0_PPD_FAST_EXIT | DDR3_MR0_WR(tWR) | in mctl_channel_init()
896 .tWR = 15, in sunxi_dram_init()
/openbmc/u-boot/board/tbs/tbs2910/
H A Dtbs2910.cfg81 /* tRCD=6+1,tRP=6+1,tRC=0x1a+1,tRAS=0x13+1,tRPA=tRP+1,tWR=7+1,tMRD=0xb+1,tCWL=4+2 */
/openbmc/u-boot/arch/arm/include/asm/
H A Demif.h1144 u8 tWR; member
1173 u32 tWR; member
/openbmc/linux/drivers/memory/samsung/
H A Dexynos5422-dmc.c1093 val = dmc->timings->tWR / clk_period_ps; in create_timings_aligned()
1094 val += dmc->timings->tWR % clk_period_ps ? 1 : 0; in create_timings_aligned()
1095 val = max(val, dmc->min_tck->tWR); in create_timings_aligned()
/openbmc/linux/arch/arm/boot/dts/samsung/
H A Dexynos5422-odroid-core.dtsi349 tWR-min-tck = <7>;
375 tWR = <7500>;
/openbmc/u-boot/board/buffalo/lsxl/
H A Dkwbimage-lschl.cfg58 # bit15-12: 4, 5 cyle tWR
H A Dkwbimage-lsxhl.cfg58 # bit15-12: 5, 6 cyle tWR
/openbmc/u-boot/board/d-link/dns325/
H A Dkwbimage.cfg55 # bit15-12: 5, 6 cyle tWR
/openbmc/u-boot/arch/arm/mach-omap2/
H A Demif-common.c704 val = max(min_tck->tWR, ns_2_cycles(timings->tWR)) - 1; in get_sdram_tim_1_reg()
/openbmc/linux/drivers/gpu/drm/amd/include/
H A Datomfirmware.h3396 uint8_t tWR; member