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Searched refs:tRAS (Results 1 – 11 of 11) sorted by relevance

/openbmc/linux/arch/arm/boot/dts/ti/omap/
H A Delpida_ecb240abacn.dtsi31 tRAS-min = <42000>;
42 tRAS-max-ns = <70000>;
53 tRAS-min = <42000>;
64 tRAS-max-ns = <70000>;
/openbmc/u-boot/arch/arm/mach-sunxi/
H A Ddram_sun9i.c117 u32 tRAS; /* in ps */ member
380 const u32 tRAS = PS2CYCLES_ROUNDUP(para->tRAS); in mctl_channel_init() local
534 (MCTL_DIV1024(tRASmax) << 8) | (MCTL_DIV2(tRAS) << 0), in mctl_channel_init()
641 writel((tRC << 26) | (tRRD << 22) | (tRAS << 16) | in mctl_channel_init()
891 .tRAS = 35000, in sunxi_dram_init()
/openbmc/linux/drivers/memory/
H A Djedec_ddr.h234 u32 tRAS; member
263 u32 tRAS; member
H A Dof_memory.c181 ret |= of_property_read_u32(np, "tRAS-min-tck", &min->tRAS); in of_lpddr3_get_min_tck()
227 ret |= of_property_read_u32(np, "tRAS", &tim->tRAS); in of_lpddr3_do_get_timings()
/openbmc/u-boot/board/buffalo/lsxl/
H A Dkwbimage-lschl.cfg55 # bit3-0: 0xf, 16 cycle tRAS (tRAS[3-0])
60 # bit20: 0, 16 cycle tRAS (tRAS[4])
H A Dkwbimage-lsxhl.cfg55 # bit3-0: 0x1, 18 cycle tRAS (tRAS[3-0])
60 # bit20: 1, 18 cycle tRAS (tRAS[4])
/openbmc/u-boot/board/d-link/dns325/
H A Dkwbimage.cfg52 # bit3-0: 1, 18 cycle tRAS (tRAS[3-0])
57 # bit20: 1, 18 cycle tRAS (tRAS[4])
/openbmc/u-boot/board/tbs/tbs2910/
H A Dtbs2910.cfg81 /* tRCD=6+1,tRP=6+1,tRC=0x1a+1,tRAS=0x13+1,tRPA=tRP+1,tWR=7+1,tMRD=0xb+1,tCWL=4+2 */
/openbmc/linux/drivers/memory/samsung/
H A Dexynos5422-dmc.c1080 val = dmc->timings->tRAS / clk_period_ps; in create_timings_aligned()
1081 val += dmc->timings->tRAS % clk_period_ps ? 1 : 0; in create_timings_aligned()
1082 val = max(val, dmc->min_tck->tRAS); in create_timings_aligned()
/openbmc/linux/arch/arm/boot/dts/samsung/
H A Dexynos5422-odroid-core.dtsi347 tRAS-min-tck = <5>;
373 tRAS = <23000>;
/openbmc/linux/drivers/gpu/drm/amd/include/
H A Datomfirmware.h3382 uint8_t tRAS; member