| /openbmc/u-boot/arch/microblaze/cpu/ |
| H A D | irq.S | 14 swi r2, r1, 4
15 swi r3, r1, 8
16 swi r4, r1, 12
17 swi r5, r1, 16
18 swi r6, r1, 20
19 swi r7, r1, 24
20 swi r8, r1, 28
21 swi r9, r1, 32
22 swi r10, r1, 36
23 swi r11, r1, 40
[all …]
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| H A D | start.S | 52 swi r6, r0, 0x28 /* used first unused MB vector */
54 swi r7, r0, 0x28
62 swi r2, r0, 0x0 /* reset address - imm opcode */
63 swi r3, r0, 0x4 /* reset address - brai opcode */
76 swi r2, r0, 0x8 /* user vector exception - imm opcode */
77 swi r3, r0, 0xC /* user vector exception - brai opcode */
109 swi r2, r0, 0x10 /* interrupt - imm opcode */
110 swi r3, r0, 0x14 /* interrupt - brai opcode */
121 swi r2, r0, 0x20 /* hardware exception - imm opcode */
122 swi r3, r0, 0x24 /* hardware exception - brai opcode */
[all …]
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| /openbmc/linux/arch/microblaze/kernel/ |
| H A D | mcount.S | 19 swi r2, r1, 4; \
20 swi r3, r1, 8; \
21 swi r4, r1, 12; \
22 swi r5, r1, 116; \
23 swi r6, r1, 16; \
24 swi r7, r1, 20; \
25 swi r8, r1, 24; \
26 swi r9, r1, 28; \
27 swi r10, r1, 32; \
28 swi r11, r1, 36; \
[all …]
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| H A D | entry.S | 180 swi r2, r1, PT_R2; /* Save SDA */ \
181 swi r3, r1, PT_R3; \
182 swi r4, r1, PT_R4; \
183 swi r5, r1, PT_R5; \
184 swi r6, r1, PT_R6; \
185 swi r7, r1, PT_R7; \
186 swi r8, r1, PT_R8; \
187 swi r9, r1, PT_R9; \
188 swi r10, r1, PT_R10; \
189 swi r11, r1, PT_R11; /* save clobbered regs after rval */\
[all …]
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| H A D | hw_exception_handler.S | 105 swi r3, r1, 4 * regnum; \
125 swi r3, r7, 4 * regnum;
316 swi r1, r0, TOPHYS(pt_pool_space + PT_R1); /* GET_SP */
320 swi r3, r1, PT_R3
321 swi r4, r1, PT_R4
322 swi r5, r1, PT_R5
323 swi r6, r1, PT_R6
325 swi r11, r1, PT_R11
326 swi r31, r1, PT_R31
331 swi r5, r1, 0;
[all …]
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| H A D | head.S | 265 swi r11, r0, TOPHYS(tlb_skip)
297 swi r11, r0, TOPHYS(tlb_skip)
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| /openbmc/linux/arch/microblaze/lib/ |
| H A D | fastcopy.S | 84 swi r9, r5, 0 /* *(d + 0) = t1 */
85 swi r10, r5, 4 /* *(d + 4) = t2 */
86 swi r11, r5, 8 /* *(d + 8) = t3 */
87 swi r12, r5, 12 /* *(d + 12) = t4 */
92 swi r9, r5, 16 /* *(d + 16) = t1 */
93 swi r10, r5, 20 /* *(d + 20) = t2 */
94 swi r11, r5, 24 /* *(d + 24) = t3 */
95 swi r12, r5, 28 /* *(d + 28) = t4 */
118 swi r9, r5, 0 /* *(d + 0) = t1 */
123 swi r9, r5, 4 /* *(d + 4) = t1 */
[all …]
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| H A D | uaccess_old.S | 25 9: swi r4 , r5, 0x0000 + offset; \
26 10: swi r19, r5, 0x0004 + offset; \
27 11: swi r20, r5, 0x0008 + offset; \
28 12: swi r21, r5, 0x000C + offset; \
29 13: swi r22, r5, 0x0010 + offset; \
30 14: swi r23, r5, 0x0014 + offset; \
31 15: swi r24, r5, 0x0018 + offset; \
32 16: swi r25, r5, 0x001C + offset; \
103 swi r5, r1, 0
104 swi r6, r1, 4
[all …]
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| H A D | modsi3.S | 20 swi r28, r1, 0
21 swi r29, r1, 4
22 swi r30, r1, 8
23 swi r31, r1, 12
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| H A D | divsi3.S | 18 swi r28, r1, 0
19 swi r29, r1, 4
20 swi r30, r1, 8
21 swi r31, r1, 12
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| H A D | udivsi3.S | 21 swi r29, r1, 0
22 swi r30, r1, 4
23 swi r31, r1, 8
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| H A D | umodsi3.S | 20 swi r29, r1, 0
21 swi r30, r1, 4
22 swi r31, r1, 8
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| /openbmc/qemu/hw/intc/ |
| H A D | riscv_aclint.c | 407 RISCVAclintSwiState *swi = opaque; in riscv_aclint_swi_read() local
409 if (addr < (swi->num_harts << 2)) { in riscv_aclint_swi_read()
410 size_t hartid = swi->hartid_base + (addr >> 2); in riscv_aclint_swi_read()
417 return (swi->sswi) ? 0 : ((env->mip & MIP_MSIP) > 0); in riscv_aclint_swi_read()
430 RISCVAclintSwiState *swi = opaque; in riscv_aclint_swi_write() local
432 if (addr < (swi->num_harts << 2)) { in riscv_aclint_swi_write()
433 size_t hartid = swi->hartid_base + (addr >> 2); in riscv_aclint_swi_write()
441 qemu_irq_raise(swi->soft_irqs[hartid - swi->hartid_base]); in riscv_aclint_swi_write()
443 if (!swi->sswi) { in riscv_aclint_swi_write()
444 qemu_irq_lower(swi->soft_irqs[hartid - swi->hartid_base]); in riscv_aclint_swi_write()
[all …]
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| H A D | omap_intc.c | 37 uint32_t swi; member
326 s->bank[i].swi = 0x00000000; in omap_inth_reset()
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| /openbmc/u-boot/arch/nds32/cpu/n1213/ag101/ |
| H A D | lowlevel_init.S | 127 swi $r1, [$r0+#0x00]
128 swi $r2, [$r0+#0x04]
201 swi $r5, [$r4 + FTSDMC021_BANK2_BSR]
202 swi $r5, [$r4 + FTSDMC021_BANK3_BSR]
244 swi.p $r7, [$r4], #4
273 swi $r6, [$r5]
285 swi $r5, [$r4]
315 swi $r7, [$r8]
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| /openbmc/linux/arch/arm/kernel/ |
| H A D | sigreturn_codes.S | 81 ARM_OK( swi #(__NR_sigreturn)|(__NR_OABI_SYSCALL_BASE) )
86 swi #0
91 ARM_OK( swi #(__NR_rt_sigreturn)|(__NR_OABI_SYSCALL_BASE) )
96 swi #0
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| /openbmc/u-boot/arch/nds32/include/asm/ |
| H A D | macro.h | 27 swi $r5, [$r4]
52 swi $r5, [$r4]
59 swi $r5, [$r4]
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| /openbmc/qemu/tests/tcg/arm/ |
| H A D | test-arm-iwmmxt.S | 39 swi #0x900004 label
41 swi #0x900001 label
|
| /openbmc/linux/drivers/net/ethernet/wangxun/ngbe/ |
| H A D | ngbe_hw.c | 50 void ngbe_sfp_modules_txrx_powerctl(struct wx *wx, bool swi) in ngbe_sfp_modules_txrx_powerctl() argument
53 wr32(wx, NGBE_GPIO_DR, swi ? 0 : NGBE_GPIO_DR_0); in ngbe_sfp_modules_txrx_powerctl()
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| H A D | ngbe_hw.h | 11 void ngbe_sfp_modules_txrx_powerctl(struct wx *wx, bool swi);
|
| /openbmc/u-boot/arch/nds32/cpu/n1213/ae3xx/ |
| H A D | lowlevel_init.S | 92 swi $r1, [$r0+#0x00]
93 swi $r2, [$r0+#0x04]
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| /openbmc/qemu/common-user/host/arm/ |
| H A D | safe-syscall.inc.S | 75 swi 0
|
| /openbmc/qemu/linux-user/arm/ |
| H A D | vdso.S | 34 swi #0
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| /openbmc/qemu/target/microblaze/ |
| H A D | insns.decode | 239 swi 111110 ..... ..... ................ @typeb
|
| /openbmc/linux/Documentation/admin-guide/device-mapper/ |
| H A D | snapshot.rst | 168 snap volumeGroup swi-a- 1.00g base 18.97
|