| /openbmc/linux/drivers/gpu/drm/amd/display/dc/link/hwss/ |
| H A D | link_hwss_dio.c | 32 struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc; in set_dio_throttled_vcp_size()
42 struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc; in setup_dio_stream_encoder()
45 pipe_ctx->stream_res.stream_enc->id, true); in setup_dio_stream_encoder()
59 struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc; in reset_dio_stream_encoder()
66 pipe_ctx->stream_res.stream_enc->id, in reset_dio_stream_encoder()
77 struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc; in setup_dio_stream_attribute()
84 pipe_ctx->stream_res.tg->inst, in setup_dio_stream_attribute()
99 pipe_ctx->stream_res.audio != NULL); in setup_dio_stream_attribute()
183 pipe_ctx->stream_res.stream_enc->funcs->dp_audio_setup( in setup_dio_audio_output()
184 pipe_ctx->stream_res.stream_enc, in setup_dio_audio_output()
[all …]
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| H A D | link_hwss_hpo_dp.c | 37 pipe_ctx->stream_res.hpo_dp_stream_enc; in set_hpo_dp_throttled_vcp_size()
51 pipe_ctx->stream_res.hpo_dp_stream_enc; in set_hpo_dp_hblank_min_symbol_width()
76 struct hpo_dp_stream_encoder *stream_enc = pipe_ctx->stream_res.hpo_dp_stream_enc; in setup_hpo_dp_stream_encoder()
85 struct hpo_dp_stream_encoder *stream_enc = pipe_ctx->stream_res.hpo_dp_stream_enc; in reset_hpo_dp_stream_encoder()
92 struct hpo_dp_stream_encoder *stream_enc = pipe_ctx->stream_res.hpo_dp_stream_enc; in setup_hpo_dp_stream_attribute()
181 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_audio_setup( in setup_hpo_dp_audio_output()
182 pipe_ctx->stream_res.hpo_dp_stream_enc, in setup_hpo_dp_audio_output()
189 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_audio_enable( in enable_hpo_dp_audio_packet()
190 pipe_ctx->stream_res.hpo_dp_stream_enc); in enable_hpo_dp_audio_packet()
195 if (pipe_ctx->stream_res.audio) in disable_hpo_dp_audio_packet()
[all …]
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn314/ |
| H A D | dcn314_hwseq.c | 97 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; in update_dsc_on_stream()
122 dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst); in update_dsc_on_stream()
124 struct display_stream_compressor *odm_dsc = odm_pipe->stream_res.dsc; in update_dsc_on_stream()
128 odm_dsc->funcs->dsc_enable(odm_dsc, odm_pipe->stream_res.opp->inst); in update_dsc_on_stream()
136 DC_LOG_DSC("Setting optc DSC config for tg instance %d:", pipe_ctx->stream_res.tg->inst); in update_dsc_on_stream()
137 pipe_ctx->stream_res.tg->funcs->set_dsc_config(pipe_ctx->stream_res.tg, in update_dsc_on_stream()
143 pipe_ctx->stream_res.tg->funcs->set_dsc_config( in update_dsc_on_stream()
144 pipe_ctx->stream_res.tg, in update_dsc_on_stream()
148 dsc->funcs->dsc_disable(pipe_ctx->stream_res.dsc); in update_dsc_on_stream()
150 ASSERT(odm_pipe->stream_res.dsc); in update_dsc_on_stream()
[all …]
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dce110/ |
| H A D | dce110_hw_sequencer.c | 638 if (pipe_ctx->stream_res.stream_enc == NULL) in dce110_update_info_frame()
648 pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets( in dce110_update_info_frame()
649 pipe_ctx->stream_res.stream_enc, in dce110_update_info_frame()
650 &pipe_ctx->stream_res.encoder_info_frame); in dce110_update_info_frame()
652 if (pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets_sdp_line_num) in dce110_update_info_frame()
653 pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets_sdp_line_num( in dce110_update_info_frame()
654 pipe_ctx->stream_res.stream_enc, in dce110_update_info_frame()
655 &pipe_ctx->stream_res.encoder_info_frame); in dce110_update_info_frame()
657 pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets( in dce110_update_info_frame()
658 pipe_ctx->stream_res.stream_enc, in dce110_update_info_frame()
[all …]
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| H A D | dce110_resource.c | 895 pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1; in get_pixel_clock_parameters()
919 get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params); in dce110_resource_build_pipe_hw_param()
922 &pipe_ctx->stream_res.pix_clk_params, in dce110_resource_build_pipe_hw_param()
1137 pipe_ctx->stream_res.tg = pool->timing_generators[underlay_idx]; in dce110_acquire_underlay()
1141 pipe_ctx->stream_res.opp = pool->opps[underlay_idx]; in dce110_acquire_underlay()
1152 pipe_ctx->stream_res.tg->inst, in dce110_acquire_underlay()
1160 pipe_ctx->stream_res.tg->funcs->program_timing(pipe_ctx->stream_res.tg, in dce110_acquire_underlay()
1169 pipe_ctx->stream_res.tg->funcs->enable_advanced_request( in dce110_acquire_underlay()
1170 pipe_ctx->stream_res.tg, in dce110_acquire_underlay()
1182 pipe_ctx->stream_res.tg->funcs->set_blank_color( in dce110_acquire_underlay()
[all …]
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn20/ |
| H A D | dcn20_hwseq.c | 111 if (pipe_ctx->stream_res.gsl_group > 0) in dcn20_setup_gsl_group_as_lock()
116 pipe_ctx->stream_res.gsl_group = group_idx; in dcn20_setup_gsl_group_as_lock()
138 group_idx = pipe_ctx->stream_res.gsl_group; in dcn20_setup_gsl_group_as_lock()
142 pipe_ctx->stream_res.gsl_group = 0; in dcn20_setup_gsl_group_as_lock()
166 if (pipe_ctx->stream_res.tg->funcs->set_gsl != NULL && in dcn20_setup_gsl_group_as_lock()
167 pipe_ctx->stream_res.tg->funcs->set_gsl_source_select != NULL) { in dcn20_setup_gsl_group_as_lock()
168 pipe_ctx->stream_res.tg->funcs->set_gsl( in dcn20_setup_gsl_group_as_lock()
169 pipe_ctx->stream_res.tg, in dcn20_setup_gsl_group_as_lock()
172 pipe_ctx->stream_res.tg->funcs->set_gsl_source_select( in dcn20_setup_gsl_group_as_lock()
173 pipe_ctx->stream_res.tg, group_idx, enable ? 4 : 0); in dcn20_setup_gsl_group_as_lock()
[all …]
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| H A D | dcn20_resource.c | 1240 pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1; in get_pixel_clock_parameters()
1278 get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params); in build_pipe_hw_param()
1282 &pipe_ctx->stream_res.pix_clk_params, in build_pipe_hw_param()
1316 … display_stream_compressor *dsc_old = dc->current_state->res_ctx.pipe_ctx[pipe_idx].stream_res.dsc; in dcn20_acquire_dsc()
1377 if (pipe_ctx->stream_res.dsc) in dcn20_add_dsc_to_stream_resource()
1380 dcn20_acquire_dsc(dc, &dc_ctx->res_ctx, &pipe_ctx->stream_res.dsc, i); in dcn20_add_dsc_to_stream_resource()
1383 if (!pipe_ctx->stream_res.dsc) { in dcn20_add_dsc_to_stream_resource()
1405 if (pipe_ctx->stream_res.dsc) in remove_dsc_from_stream_resource()
1406 dcn20_release_dsc(&new_ctx->res_ctx, dc->res_pool, &pipe_ctx->stream_res.dsc); in remove_dsc_from_stream_resource()
1480 next_odm_pipe->stream_res.dsc = NULL; in dcn20_split_stream_for_odm()
[all …]
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn31/ |
| H A D | dcn31_hwseq.c | 381 if (pipe_ctx->stream_res.stream_enc == NULL) in dcn31_update_info_frame()
391 pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets( in dcn31_update_info_frame()
392 pipe_ctx->stream_res.stream_enc, in dcn31_update_info_frame()
393 &pipe_ctx->stream_res.encoder_info_frame); in dcn31_update_info_frame()
395 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->update_dp_info_packets( in dcn31_update_info_frame()
396 pipe_ctx->stream_res.hpo_dp_stream_enc, in dcn31_update_info_frame()
397 &pipe_ctx->stream_res.encoder_info_frame); in dcn31_update_info_frame()
400 if (pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets_sdp_line_num) in dcn31_update_info_frame()
401 pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets_sdp_line_num( in dcn31_update_info_frame()
402 pipe_ctx->stream_res.stream_enc, in dcn31_update_info_frame()
[all …]
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn10/ |
| H A D | dcn10_hw_sequencer.c | 105 tg = pipe_ctx->stream_res.tg; in dcn10_lock_all_pipes()
539 struct timing_generator *tg = pipe_ctx->stream_res.tg; in dcn10_did_underflow_occur()
922 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, true); in dcn10_enable_stream_timing()
926 &pipe_ctx->stream_res.pix_clk_params, in dcn10_enable_stream_timing()
941 pipe_ctx->stream_res.tg->funcs->program_timing( in dcn10_enable_stream_timing()
942 pipe_ctx->stream_res.tg, in dcn10_enable_stream_timing()
955 inst_offset = reg_offsets[pipe_ctx->stream_res.tg->inst].fmt; in dcn10_enable_stream_timing()
957 pipe_ctx->stream_res.opp->funcs->opp_program_fmt( in dcn10_enable_stream_timing()
958 pipe_ctx->stream_res.opp, in dcn10_enable_stream_timing()
974 if (pipe_ctx->stream_res.tg->funcs->set_blank_color) in dcn10_enable_stream_timing()
[all …]
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/link/accessories/ |
| H A D | link_dp_cts.c | 430 struct output_pixel_processor *opp = pipe_ctx->stream_res.opp; in set_crtc_test_pattern()
485 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern) { in set_crtc_test_pattern()
487 pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg, in set_crtc_test_pattern()
513 odm_opp = odm_pipe->stream_res.opp; in set_crtc_test_pattern()
527 odm_opp = odm_pipe->stream_res.opp; in set_crtc_test_pattern()
546 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern) { in set_crtc_test_pattern()
548 pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg, in set_crtc_test_pattern()
556 odm_opp = odm_pipe->stream_res.opp; in set_crtc_test_pattern()
570 odm_opp = odm_pipe->stream_res.opp; in set_crtc_test_pattern()
881 if (pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_enable) { in dp_set_test_pattern()
[all …]
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| H A D | link_fpga.c | 73 …proposed_table.stream_allocations[i].hpo_dp_stream_enc = state->res_ctx.pipe_ctx[i].stream_res.hpo… in dp_fpga_hpo_enable_link_and_stream()
82 proposed_table.stream_allocations[0].hpo_dp_stream_enc = pipe_ctx->stream_res.hpo_dp_stream_enc; in dp_fpga_hpo_enable_link_and_stream()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn32/ |
| H A D | dcn32_hwseq.c | 402 pipe->stream_res.tg->funcs->wait_for_state(pipe->stream_res.tg, CRTC_STATE_VBLANK); in dcn32_subvp_pipe_control_lock()
444 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; in dcn32_set_mpc_shaper_3dlut()
480 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; in dcn32_set_mcm_luts()
554 if (pipe_ctx->stream_res.opp && in dcn32_set_input_transfer_func()
555 pipe_ctx->stream_res.opp->ctx && in dcn32_set_input_transfer_func()
567 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; in dcn32_set_output_transfer_func()
1005 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; in update_dsc_on_stream()
1030 dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst); in update_dsc_on_stream()
1032 struct display_stream_compressor *odm_dsc = odm_pipe->stream_res.dsc; in update_dsc_on_stream()
1036 odm_dsc->funcs->dsc_enable(odm_dsc, odm_pipe->stream_res.opp->inst); in update_dsc_on_stream()
[all …]
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| H A D | dcn32_resource_helpers.c | 146 if (pipe->stream_res.dsc) in dcn32_merge_pipes_for_subvp()
147 dcn20_release_dsc(&context->res_ctx, dc->res_pool, &pipe->stream_res.dsc); in dcn32_merge_pipes_for_subvp()
149 memset(&pipe->stream_res, 0, sizeof(pipe->stream_res)); in dcn32_merge_pipes_for_subvp()
163 memset(&pipe->stream_res, 0, sizeof(pipe->stream_res)); in dcn32_merge_pipes_for_subvp()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dce/ |
| H A D | dce_hwseq.c | 56 if (lock && pipe->stream_res.tg->funcs->is_blanked && in dce_pipe_control_lock()
57 pipe->stream_res.tg->funcs->is_blanked(pipe->stream_res.tg)) in dce_pipe_control_lock()
60 val = REG_GET_4(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst], in dce_pipe_control_lock()
71 REG_SET_2(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst], val, in dce_pipe_control_lock()
76 REG_SET_2(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst], val, in dce_pipe_control_lock()
82 uint32_t value = REG_READ(CRTC_H_BLANK_START_END[pipe->stream_res.tg->inst]); in dce_pipe_control_lock()
83 REG_WRITE(CRTC_H_BLANK_START_END[pipe->stream_res.tg->inst], value); in dce_pipe_control_lock()
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| H A D | dmub_psr.c | 349 if (pipe_ctx->stream_res.opp) in dmub_psr_copy_settings()
350 copy_settings_data->opp_inst = pipe_ctx->stream_res.opp->inst; in dmub_psr_copy_settings()
353 if (pipe_ctx->stream_res.tg) in dmub_psr_copy_settings()
354 copy_settings_data->otg_inst = pipe_ctx->stream_res.tg->inst; in dmub_psr_copy_settings()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/link/ |
| H A D | link_dpms.c | 666 config.otg_inst = (uint8_t) pipe_ctx->stream_res.tg->inst; in update_psp_stream_config()
669 config.dig_fe = (uint8_t) pipe_ctx->stream_res.stream_enc->stream_enc_inst; in update_psp_stream_config()
672 config.stream_enc_idx = pipe_ctx->stream_res.stream_enc->id - ENGINE_ID_DIGA; in update_psp_stream_config()
675 pipe_ctx->stream_res.hpo_dp_stream_enc->id - ENGINE_ID_HPO_DP_0; in update_psp_stream_config()
777 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; in link_set_dsc_on_stream()
802 dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst); in link_set_dsc_on_stream()
804 struct display_stream_compressor *odm_dsc = odm_pipe->stream_res.dsc; in link_set_dsc_on_stream()
807 odm_dsc->funcs->dsc_enable(odm_dsc, odm_pipe->stream_res.opp->inst); in link_set_dsc_on_stream()
816 …DC_LOG_DSC("Setting stream encoder DSC config for engine %d:", (int)pipe_ctx->stream_res.stream_en… in link_set_dsc_on_stream()
818 pipe_ctx->stream_res.stream_enc->funcs->dp_set_dsc_config(pipe_ctx->stream_res.stream_enc, in link_set_dsc_on_stream()
[all …]
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn30/ |
| H A D | dcn30_hwseq.c | 98 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; in dcn30_set_mpc_shaper_3dlut()
178 if (pipe_ctx->stream_res.opp && pipe_ctx->stream_res.opp->ctx) { in dcn30_set_input_transfer_func()
194 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; in dcn30_set_output_transfer_func()
627 if (dc_is_hdmi_signal(pipe_ctx->stream->signal) && pipe_ctx->stream_res.stream_enc != NULL) { in dcn30_set_avmute()
628 pipe_ctx->stream_res.stream_enc->funcs->set_avmute( in dcn30_set_avmute()
629 pipe_ctx->stream_res.stream_enc, in dcn30_set_avmute()
634 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VACTIVE); in dcn30_set_avmute()
635 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VBLANK); in dcn30_set_avmute()
636 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VACTIVE); in dcn30_set_avmute()
637 pipe_ctx->stream_res.tg->funcs->wait_for_state(pipe_ctx->stream_res.tg, CRTC_STATE_VBLANK); in dcn30_set_avmute()
[all …]
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn201/ |
| H A D | dcn201_hwseq.c | 307 pipe_ctx->stream_res.tg = tg; in dcn201_init_hw()
316 pipe_ctx->stream_res.opp = NULL; in dcn201_init_hw()
321 pipe_ctx->stream_res.opp = res_pool->opps[i]; in dcn201_init_hw()
342 pipe_ctx->stream_res.tg = NULL; in dcn201_init_hw()
380 struct output_pixel_processor *opp = pipe_ctx->stream_res.opp; in dcn201_plane_atomic_disconnect()
427 struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params); in dcn201_update_mpcc()
517 hubp->opp_id = pipe_ctx->stream_res.opp->inst; in dcn201_update_mpcc()
538 pipe->stream_res.tg->funcs->triplebuffer_lock(pipe->stream_res.tg); in dcn201_pipe_control_lock()
540 pipe->stream_res.tg->funcs->triplebuffer_unlock(pipe->stream_res.tg); in dcn201_pipe_control_lock()
543 pipe->stream_res.tg->funcs->lock(pipe->stream_res.tg); in dcn201_pipe_control_lock()
[all …]
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/core/ |
| H A D | dc_resource.c | 1817 split_pipe->stream_res.tg = pool->timing_generators[i]; in acquire_first_split_pipe()
1821 split_pipe->stream_res.opp = pool->opps[i]; in acquire_first_split_pipe()
2340 pipe_ctx->stream_res.tg = pool->timing_generators[i]; in acquire_first_free_pipe()
2346 pipe_ctx->stream_res.opp = pool->opps[i]; in acquire_first_free_pipe()
2354 pipe_ctx->stream_res.tg = pool->timing_generators[tg_inst]; in acquire_first_free_pipe()
2355 pipe_ctx->stream_res.opp = pool->opps[tg_inst]; in acquire_first_free_pipe()
2466 ASSERT(del_pipe->stream_res.stream_enc); in dc_remove_stream_from_ctx()
2470 del_pipe->stream_res.stream_enc, in dc_remove_stream_from_ctx()
2476 del_pipe->stream_res.hpo_dp_stream_enc, in dc_remove_stream_from_ctx()
2481 if (del_pipe->stream_res in dc_remove_stream_from_ctx()
[all...] |
| H A D | dc.c | 419 if (pipe->stream == stream && pipe->stream_res.tg) { in dc_stream_adjust_vmin_vmax()
454 if (pipe->stream == stream && pipe->stream_res.tg) { in dc_stream_get_last_used_drr_vtotal()
458 if (pipe->stream_res.tg->funcs->get_last_used_drr_vtotal) { in dc_stream_get_last_used_drr_vtotal()
459 pipe->stream_res.tg->funcs->get_last_used_drr_vtotal(pipe->stream_res.tg, refresh_rate); in dc_stream_get_last_used_drr_vtotal()
485 if (pipe->stream == stream && pipe->stream_res.stream_enc) { in dc_stream_get_crtc_position()
553 mux_mapping.otg_output_num = pipe->stream_res.tg->inst; in dc_stream_forward_crc_window()
629 tg = pipe->stream_res.tg; in dc_stream_configure_crc()
668 tg = pipe->stream_res.tg; in dc_stream_get_crc()
687 pipe_ctx->stream_res.opp->dyn_expansion = option; in dc_stream_set_dyn_expansion()
688 pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion( in dc_stream_set_dyn_expansion()
[all …]
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dce60/ |
| H A D | dce60_hw_sequencer.c | 128 params.inst = pipe_ctx->stream_res.tg->inst; in dce60_enable_fbc()
192 pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, blank_target); in dce60_program_surface_visibility()
200 uint32_t color_value = MAX_TG_COLOR_VALUE * (4 - pipe_ctx->stream_res.tg->inst) / 4; in dce60_get_surface_visual_confirm_color()
251 if (pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color) { in dce60_program_scaler()
260 pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color( in dce60_program_scaler()
261 pipe_ctx->stream_res.tg, in dce60_program_scaler()
|
| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn21/ |
| H A D | dcn21_hwseq.c | 181 struct abm *abm = pipe_ctx->stream_res.abm; in dcn21_set_abm_immediate_disable()
182 uint32_t otg_inst = pipe_ctx->stream_res.tg->inst; in dcn21_set_abm_immediate_disable()
208 struct abm *abm = pipe_ctx->stream_res.abm; in dcn21_set_pipe()
209 struct timing_generator *tg = pipe_ctx->stream_res.tg; in dcn21_set_pipe()
243 struct abm *abm = pipe_ctx->stream_res.abm; in dcn21_set_backlight_level()
244 struct timing_generator *tg = pipe_ctx->stream_res.tg; in dcn21_set_backlight_level()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/ |
| H A D | dce_clk_mgr.c | 180 if (pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz / 10 > max_pix_clk) in dce_get_max_pixel_clock_for_all_paths()
181 max_pix_clk = pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz / 10; in dce_get_max_pixel_clock_for_all_paths()
187 pipe_ctx->stream_res.pix_clk_params.requested_sym_clk > max_pix_clk) in dce_get_max_pixel_clock_for_all_paths()
188 max_pix_clk = pipe_ctx->stream_res.pix_clk_params.requested_sym_clk; in dce_get_max_pixel_clock_for_all_paths()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/ |
| H A D | dcn316_clk_mgr.c | 118 if (pipe->stream_res.tg && pipe->stream_res.tg->funcs->immediate_disable_crtc) in dcn316_disable_otg_wa()
119 pipe->stream_res.tg->funcs->immediate_disable_crtc(pipe->stream_res.tg); in dcn316_disable_otg_wa()
123 pipe->stream_res.tg->funcs->enable_crtc(pipe->stream_res.tg); in dcn316_disable_otg_wa()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/ |
| H A D | dcn32_clk_mgr.c | 258 if (pipe_ctx->stream_res.tg && in dcn32_update_clocks_update_dtb_dto()
259 !(tg_mask & (1 << pipe_ctx->stream_res.tg->inst))) { in dcn32_update_clocks_update_dtb_dto()
260 tg_mask |= (1 << pipe_ctx->stream_res.tg->inst); in dcn32_update_clocks_update_dtb_dto()
262 dto_params.otg_inst = pipe_ctx->stream_res.tg->inst; in dcn32_update_clocks_update_dtb_dto()
354 struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc; in dcn32_update_clocks_update_dentist()
372 pipe_ctx->stream_res.tg->inst); in dcn32_update_clocks_update_dentist()
399 struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc; in dcn32_update_clocks_update_dentist()
415 pipe_ctx->stream_res.tg->inst); in dcn32_update_clocks_update_dentist()
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