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Searched refs:spr_cb (Results 1 – 14 of 14) sorted by relevance

/openbmc/qemu/target/ppc/
H A Dgdbstub.c308 for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) { in gdb_gen_spr_feature()
309 ppc_spr_t *spr = &env->spr_cb[i]; in gdb_gen_spr_feature()
335 for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) { in gdb_gen_spr_feature()
336 ppc_spr_t *spr = &env->spr_cb[i]; in gdb_gen_spr_feature()
356 for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) { in gdb_find_spr_idx()
357 ppc_spr_t *spr = &env->spr_cb[i]; in gdb_find_spr_idx()
H A Dppc-qmp-cmds.c157 for (i = 0; i < ARRAY_SIZE(env->spr_cb); ++i) { in target_get_monitor_def()
158 ppc_spr_t *spr = &env->spr_cb[i]; in target_get_monitor_def()
H A Dtranslate.c199 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ member
4087 read_cb = ctx->spr_cb[sprn].uea_read; in gen_op_mfspr()
4090 read_cb = ctx->spr_cb[sprn].uea_read; in gen_op_mfspr()
4092 read_cb = ctx->spr_cb[sprn].hea_read; in gen_op_mfspr()
4094 read_cb = ctx->spr_cb[sprn].oea_read; in gen_op_mfspr()
4271 write_cb = ctx->spr_cb[sprn].uea_write; in gen_mtspr()
4274 write_cb = ctx->spr_cb[sprn].uea_write; in gen_mtspr()
4276 write_cb = ctx->spr_cb[sprn].hea_write; in gen_mtspr()
4278 write_cb = ctx->spr_cb[sprn].oea_write; in gen_mtspr()
6481 ctx->spr_cb = env->spr_cb; in ppc_tr_init_disas_context()
H A Dmachine.c233 env->spr[SPR_PVR] = env->spr_cb[SPR_PVR].default_value; in cpu_post_load()
H A Dhelper_regs.c407 ppc_spr_t *spr = &env->spr_cb[num]; in _spr_register()
H A Dcpu.h1288 ppc_spr_t spr_cb[1024]; member
2982 return cpu->env.spr_cb[spr].name != NULL; in ppc_has_spr()
H A Dkvm.c973 uint64_t id = env->spr_cb[i].one_reg_id; in kvm_arch_put_registers()
1273 uint64_t id = env->spr_cb[i].one_reg_id; in kvm_arch_get_registers()
H A Dcpu_init.c7274 for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) { in ppc_cpu_reset_hold()
7275 ppc_spr_t *spr = &env->spr_cb[i]; in ppc_cpu_reset_hold()
7676 if (env->spr_cb[SPR_LPCR].name) { in ppc_cpu_dump_state()
7690 if (env->spr_cb[SPR_SDR1].name) { /* SDR1 Exists */ in ppc_cpu_dump_state()
7693 if (env->spr_cb[SPR_PTCR].name) { /* PTCR Exists */ in ppc_cpu_dump_state()
/openbmc/qemu/hw/ppc/
H A Dspapr_cpu_core.c273 env->spr_cb[SPR_PIR].default_value = cs->cpu_index; in spapr_realize_vcpu()
274 env->spr_cb[SPR_TIR].default_value = thread_index; in spapr_realize_vcpu()
H A Dpnv_core.c303 ppc_spr_t *pir_spr = &env->spr_cb[SPR_PIR]; in pnv_core_cpu_realize()
304 ppc_spr_t *tir_spr = &env->spr_cb[SPR_TIR]; in pnv_core_cpu_realize()
H A Dppc.c1519 return env->spr_cb[SPR_PIR].default_value; in ppc_cpu_pir()
1525 return env->spr_cb[SPR_TIR].default_value; in ppc_cpu_tir()
H A De500.c968 env->spr_cb[SPR_BOOKE_PIR].default_value = cs->cpu_index = i; in ppce500_init()
/openbmc/qemu/hw/intc/
H A Dxive2.c278 uint32_t pir = env->spr_cb[SPR_PIR].default_value; in xive2_tctx_save_ctx()
345 uint32_t pir = env->spr_cb[SPR_PIR].default_value; in xive2_tctx_hw_cam_line()
516 uint32_t pir = env->spr_cb[SPR_PIR].default_value; in xive2_tctx_restore_os_ctx()
H A Dxive.c1657 uint32_t pir = env->spr_cb[SPR_PIR].default_value; in xive_tctx_hw_cam_line()