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Searched refs:simd (Results 1 – 25 of 39) sorted by relevance

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/openbmc/openbmc/poky/meta/conf/machine/include/arm/
H A Darch-armv8r.inc18 …ES += "armv8r armv8r-crc armv8r-crypto armv8r-simd armv8r-crc-crypto armv8r-crc-simd armv8r-crc-cr…
22 ARMPKGARCH:tune-armv8r-simd = "armv8r"
24 ARMPKGARCH:tune-armv8r-crc-simd = "armv8r"
25 ARMPKGARCH:tune-armv8r-crc-crypto-simd = "armv8r"
29 TUNE_FEATURES:tune-armv8r-simd = "${TUNE_FEATURES:tune-armv8r} simd"
31 TUNE_FEATURES:tune-armv8r-crc-simd = "${TUNE_FEATURES:tune-armv8r-crc} simd"
32 TUNE_FEATURES:tune-armv8r-crc-crypto-simd = "${TUNE_FEATURES:tune-armv8r-crc-crypto} simd"
36 PACKAGE_EXTRA_ARCHS:tune-armv8r-simd = "${PACKAGE_EXTRA_ARCHS:tune-armv8r} armv8r-simd"
37 PACKAGE_EXTRA_ARCHS:tune-armv8r-crc-simd = "${PACKAGE_EXTRA_ARCHS:tune-armv8r-crc} armv8r-si…
38 …AGE_EXTRA_ARCHS:tune-armv8r-crc-crypto-simd = "${PACKAGE_EXTRA_ARCHS:tune-armv8r-crc-simd} armv8r-…
H A Dfeature-arm-simd.inc4 TUNEVALID[simd] = "Enable instructions for Advanced SIMD and floating-point units"
5 TUNE_CCARGS_MARCH_OPTS .= "${@bb.utils.contains('TUNE_FEATURES', 'simd', '+simd', '', d)}"
H A Dfeature-arm-vfp.inc8 # simd is special, we don't pass this to the -mfpu, it's implied
14 …d.getVar('TUNE_CCARGS_MFPU') != '' or bb.utils.contains('TUNE_FEATURES', 'simd', True, False, d)) …
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-support/fftw/fftw/
H A D0001-NEON-autodetection-segfaults-assume-neon-present.patch15 simd-support/neon.c | 46 +---------------------------------------------
18 diff --git a/simd-support/neon.c b/simd-support/neon.c
20 --- a/simd-support/neon.c
21 +++ b/simd-support/neon.c
/openbmc/linux/crypto/
H A Dsimd.c215 struct simd_skcipher_alg *simd; in simd_register_skciphers_compat() local
227 simd = simd_skcipher_create_compat(algs + i, algname, drvname, basename); in simd_register_skciphers_compat()
228 err = PTR_ERR(simd); in simd_register_skciphers_compat()
229 if (IS_ERR(simd)) in simd_register_skciphers_compat()
231 simd_algs[i] = simd; in simd_register_skciphers_compat()
438 struct simd_aead_alg *simd; in simd_register_aeads_compat() local
450 simd = simd_aead_create_compat(algs + i, algname, drvname, basename); in simd_register_aeads_compat()
451 err = PTR_ERR(simd); in simd_register_aeads_compat()
452 if (IS_ERR(simd)) in simd_register_aeads_compat()
454 simd_algs[i] = simd; in simd_register_aeads_compat()
H A DMakefile209 crypto_simd-y := simd.o
/openbmc/openbmc/poky/meta/recipes-devtools/rsync/
H A Drsync_3.4.1.bb43 #| ./simd-checksum-x86_64.cpp: In function 'uint32_t get_checksum1_cpp(char*, int32_t)':
44 #| ./simd-checksum-x86_64.cpp:89:52: error: multiversioning needs 'ifunc' which is not supported on…
47 #| ./simd-checksum-x86_64.cpp:480:1: error: use of multiversioned function without a default
50 #| If you can't fix the issue, re-run ./configure with --disable-roll-simd.
51 EXTRA_OECONF:append:libc-musl = " --disable-roll-simd"
/openbmc/openbmc/poky/meta/conf/machine/include/arm/armv8r/
H A Dtune-cortexr82.inc13 TUNE_FEATURES:tune-cortexr82 = "${TUNE_FEATURES:tune-armv8r-crc-simd} cortex…
14 PACKAGE_EXTRA_ARCHS:tune-cortexr82 = "${PACKAGE_EXTRA_ARCHS:tune-armv8r-crc-simd} …
H A Dtune-cortexr52.inc14 TUNE_FEATURES:tune-cortexr52 = "aarch64 crc simd cortexr52"
15 PACKAGE_EXTRA_ARCHS:tune-cortexr52 = "${PACKAGE_EXTRA_ARCHS:tune-armv8r-crc-simd} cortexr52"
/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v9_4_2.c422 uint32_t se, cu, simd, wave; in gfx_v9_4_2_log_wave_assignment() local
437 for (simd = 0; simd < SIMD_ID_MAX; simd++) { in gfx_v9_4_2_log_wave_assignment()
456 uint32_t se, cu, simd, wave; in gfx_v9_4_2_wait_for_waves_assigned() local
467 for (simd = 0; simd < SIMD_ID_MAX; simd++) in gfx_v9_4_2_wait_for_waves_assigned()
1806 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t ad… in wave_read_ind() argument
1810 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | in wave_read_ind()
1820 uint32_t i, simd, wave; in gfx_v9_4_2_log_cu_timeout_status() local
1831 simd = i / cu_info->max_waves_per_simd; in gfx_v9_4_2_log_cu_timeout_status()
1834 wave_status = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); in gfx_v9_4_2_log_cu_timeout_status()
1835 wave_pc_lo = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); in gfx_v9_4_2_log_cu_timeout_status()
[all …]
H A Dgfx_v9_4_3.c550 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t … in wave_read_ind() argument
554 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | in wave_read_ind()
560 static void wave_read_regs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, in wave_read_regs() argument
566 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | in wave_read_regs()
576 uint32_t xcc_id, uint32_t simd, uint32_t wave, in gfx_v9_4_3_read_wave_data() argument
581 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_STATUS); in gfx_v9_4_3_read_wave_data()
582 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_LO); in gfx_v9_4_3_read_wave_data()
583 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_PC_HI); in gfx_v9_4_3_read_wave_data()
584 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_LO); in gfx_v9_4_3_read_wave_data()
585 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, simd, wave, ixSQ_WAVE_EXEC_HI); in gfx_v9_4_3_read_wave_data()
[all …]
H A Dgfx_v6_0.c2946 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t ad… in wave_read_ind() argument
2950 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | in wave_read_ind()
2956 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd, in wave_read_regs() argument
2962 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | in wave_read_regs()
2971 static void gfx_v6_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uin… in gfx_v6_0_read_wave_data() argument
2975 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); in gfx_v6_0_read_wave_data()
2976 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); in gfx_v6_0_read_wave_data()
2977 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); in gfx_v6_0_read_wave_data()
2978 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); in gfx_v6_0_read_wave_data()
2979 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); in gfx_v6_0_read_wave_data()
[all …]
H A Dgfx_v7_0.c4087 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t ad… in wave_read_ind() argument
4091 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | in wave_read_ind()
4097 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd, in wave_read_regs() argument
4103 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | in wave_read_regs()
4112 static void gfx_v7_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uin… in gfx_v7_0_read_wave_data() argument
4116 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); in gfx_v7_0_read_wave_data()
4117 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); in gfx_v7_0_read_wave_data()
4118 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); in gfx_v7_0_read_wave_data()
4119 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); in gfx_v7_0_read_wave_data()
4120 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); in gfx_v7_0_read_wave_data()
[all …]
H A Damdgpu_umr.h50 u32 gpr_or_wave, se, sh, cu, wave, simd, xcc_id; member
H A Damdgpu_debugfs.c434 adev->gfx.funcs->read_wave_data(adev, rd->id.xcc_id, rd->id.simd, rd->id.wave, data, &x); in amdgpu_debugfs_gprwave_read()
439 …adev->gfx.funcs->read_wave_vgprs(adev, rd->id.xcc_id, rd->id.simd, rd->id.wave, rd->id.gpr.thread,… in amdgpu_debugfs_gprwave_read()
442 …adev->gfx.funcs->read_wave_sgprs(adev, rd->id.xcc_id, rd->id.simd, rd->id.wave, *pos, size>>2, dat… in amdgpu_debugfs_gprwave_read()
1054 uint32_t offset, se, sh, cu, wave, simd, data[32]; in amdgpu_debugfs_wave_read() local
1065 simd = (*pos & GENMASK_ULL(44, 37)) >> 37; in amdgpu_debugfs_wave_read()
1085 adev->gfx.funcs->read_wave_data(adev, 0, simd, wave, data, &x); in amdgpu_debugfs_wave_read()
1146 uint32_t offset, se, sh, cu, wave, simd, thread, bank, *data; in amdgpu_debugfs_gpr_read() local
1157 simd = (*pos & GENMASK_ULL(51, 44)) >> 44; in amdgpu_debugfs_gpr_read()
1179 adev->gfx.funcs->read_wave_vgprs(adev, 0, simd, wave, thread, offset, size>>2, data); in amdgpu_debugfs_gpr_read()
1182 adev->gfx.funcs->read_wave_sgprs(adev, 0, simd, wave, offset, size>>2, data); in amdgpu_debugfs_gpr_read()
H A Damdgpu_gfx.h287 void (*read_wave_data)(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,
289 void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,
292 void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,
H A Dgfx_v8_0.c5193 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t ad… in wave_read_ind() argument
5197 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | in wave_read_ind()
5203 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd, in wave_read_regs() argument
5209 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | in wave_read_regs()
5218 static void gfx_v8_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uin… in gfx_v8_0_read_wave_data() argument
5222 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); in gfx_v8_0_read_wave_data()
5223 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); in gfx_v8_0_read_wave_data()
5224 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); in gfx_v8_0_read_wave_data()
5225 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); in gfx_v8_0_read_wave_data()
5226 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); in gfx_v8_0_read_wave_data()
[all …]
H A Dgfx_v9_0.c1746 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t ad… in wave_read_ind() argument
1750 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | in wave_read_ind()
1756 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd, in wave_read_regs() argument
1762 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) | in wave_read_regs()
1771 static void gfx_v9_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uin… in gfx_v9_0_read_wave_data() argument
1775 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS); in gfx_v9_0_read_wave_data()
1776 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO); in gfx_v9_0_read_wave_data()
1777 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI); in gfx_v9_0_read_wave_data()
1778 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO); in gfx_v9_0_read_wave_data()
1779 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI); in gfx_v9_0_read_wave_data()
[all …]
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-extended/minifi-cpp/files/
H A D0008-libsodium-aarch64_crypto.patch20 -#pragma GCC target("+simd+crypto")
33 +#pragma GCC target("+simd+crypto")
/openbmc/linux/arch/arm/crypto/
H A Daes-neonbs-glue.c521 struct simd_skcipher_alg *simd; in aes_init() local
542 simd = simd_skcipher_create_compat(aes_algs + i, algname, drvname, basename); in aes_init()
543 err = PTR_ERR(simd); in aes_init()
544 if (IS_ERR(simd)) in aes_init()
547 aes_simd_algs[i] = simd; in aes_init()
H A Daes-ce-glue.c696 struct simd_skcipher_alg *simd; in aes_init() local
714 simd = simd_skcipher_create_compat(aes_algs + i, algname, drvname, basename); in aes_init()
715 err = PTR_ERR(simd); in aes_init()
716 if (IS_ERR(simd)) in aes_init()
719 aes_simd_algs[i] = simd; in aes_init()
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-extended/minio/
H A Dsrc_uri.inc86 # github.com/minio/md5-simd v1.1.2
87 # [1] git ls-remote https://github.com/minio/md5-simd 776275e0c9a74ceebbd50fe5c1d61b0c80c608df
88 SRCREV_md5-simd = "776275e0c9a74ceebbd50fe5c1d61b0c80c608df"
89 ….com/minio/md5-simd;name=md5-simd;protocol=https;nobranch=1;destsuffix=${WORKDIR}/${BP}/src/import…
106 # github.com/minio/sha256-simd v1.0.0
107 # [1] git ls-remote https://github.com/minio/sha256-simd 6a57409d8e0fa3ae883aee331b71aaa40d5a7dd9
108 SRCREV_sha256-simd = "6a57409d8e0fa3ae883aee331b71aaa40d5a7dd9"
109 …inio/sha256-simd;name=sha256-simd;protocol=https;nobranch=1;destsuffix=${WORKDIR}/${BP}/src/import…
H A Dminio_git.bb60 github.com/minio/md5-simd:github.com/minio/md5-simd \
64 github.com/minio/sha256-simd:github.com/minio/sha256-simd \
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-extended/minio/minio/
H A Dmodules.txt35 # github.com/minio/md5-simd v1.1.2
43 # github.com/minio/sha256-simd v1.0.0
/openbmc/linux/include/asm-generic/
H A DKbuild53 mandatory-y += simd.h

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