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Searched refs:sh_num (Results 1 – 21 of 21) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dsoc21.c272 u32 sh_num, u32 reg_offset) in soc21_read_indexed_register() argument
277 if (se_num != 0xffffffff || sh_num != 0xffffffff) in soc21_read_indexed_register()
278 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0); in soc21_read_indexed_register()
282 if (se_num != 0xffffffff || sh_num != 0xffffffff) in soc21_read_indexed_register()
290 u32 sh_num, u32 reg_offset) in soc21_get_register_value() argument
293 return soc21_read_indexed_register(adev, se_num, sh_num, reg_offset); in soc21_get_register_value()
302 u32 sh_num, u32 reg_offset, u32 *value) in soc21_read_register() argument
318 se_num, sh_num, reg_offset); in soc21_read_register()
H A Dnv.c359 u32 sh_num, u32 reg_offset) in nv_read_indexed_register() argument
364 if (se_num != 0xffffffff || sh_num != 0xffffffff) in nv_read_indexed_register()
365 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0); in nv_read_indexed_register()
369 if (se_num != 0xffffffff || sh_num != 0xffffffff) in nv_read_indexed_register()
377 u32 sh_num, u32 reg_offset) in nv_get_register_value() argument
380 return nv_read_indexed_register(adev, se_num, sh_num, reg_offset); in nv_get_register_value()
389 u32 sh_num, u32 reg_offset, u32 *value) in nv_read_register() argument
405 se_num, sh_num, reg_offset); in nv_read_register()
H A Dgfx_v9_0.h29 void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num,
H A Dsoc15.c381 u32 sh_num, u32 reg_offset) in soc15_read_indexed_register() argument
386 if (se_num != 0xffffffff || sh_num != 0xffffffff) in soc15_read_indexed_register()
387 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0); in soc15_read_indexed_register()
391 if (se_num != 0xffffffff || sh_num != 0xffffffff) in soc15_read_indexed_register()
399 u32 sh_num, u32 reg_offset) in soc15_get_register_value() argument
402 return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset); in soc15_get_register_value()
413 u32 sh_num, u32 reg_offset, u32 *value) in soc15_read_register() argument
429 se_num, sh_num, reg_offset); in soc15_read_register()
H A Dcik.c1124 u32 sh_num, u32 reg_offset) in cik_get_register_value() argument
1129 unsigned sh_idx = (sh_num == 0xffffffff) ? 0 : sh_num; in cik_get_register_value()
1143 if (se_num != 0xffffffff || sh_num != 0xffffffff) in cik_get_register_value()
1144 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0); in cik_get_register_value()
1148 if (se_num != 0xffffffff || sh_num != 0xffffffff) in cik_get_register_value()
1219 u32 sh_num, u32 reg_offset, u32 *value) in cik_read_register() argument
1230 *value = cik_get_register_value(adev, indexed, se_num, sh_num, in cik_read_register()
H A Dvi.c747 u32 sh_num, u32 reg_offset) in vi_get_register_value() argument
752 unsigned sh_idx = (sh_num == 0xffffffff) ? 0 : sh_num; in vi_get_register_value()
766 if (se_num != 0xffffffff || sh_num != 0xffffffff) in vi_get_register_value()
767 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0); in vi_get_register_value()
771 if (se_num != 0xffffffff || sh_num != 0xffffffff) in vi_get_register_value()
842 u32 sh_num, u32 reg_offset, u32 *value) in vi_read_register() argument
853 *value = vi_get_register_value(adev, indexed, se_num, sh_num, in vi_read_register()
H A Dsi.c1166 u32 sh_num, u32 reg_offset) in si_get_register_value() argument
1171 unsigned sh_idx = (sh_num == 0xffffffff) ? 0 : sh_num; in si_get_register_value()
1183 if (se_num != 0xffffffff || sh_num != 0xffffffff) in si_get_register_value()
1184 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0); in si_get_register_value()
1188 if (se_num != 0xffffffff || sh_num != 0xffffffff) in si_get_register_value()
1240 u32 sh_num, u32 reg_offset, u32 *value) in si_read_register() argument
1251 *value = si_get_register_value(adev, indexed, se_num, sh_num, in si_read_register()
H A Damdgpu_kms.c732 unsigned int sh_num = (info->read_mmr_reg.instance >> in amdgpu_info_ioctl() local
749 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK) { in amdgpu_info_ioctl()
750 sh_num = 0xffffffff; in amdgpu_info_ioctl()
751 } else if (sh_num >= AMDGPU_GFX_MAX_SH_PER_SE) { in amdgpu_info_ioctl()
771 if (amdgpu_asic_read_register(adev, se_num, sh_num, in amdgpu_info_ioctl()
H A Dgfx_v9_4.c94 u32 sh_num, u32 instance) in gfx_v9_4_select_se_sh() argument
111 if (sh_num == 0xffffffff) in gfx_v9_4_select_se_sh()
115 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); in gfx_v9_4_select_se_sh()
H A Damdgpu_gfx.h286 u32 sh_num, u32 instance, int xcc_id);
H A Dgfx_v6_0.c1288 u32 sh_num, u32 instance, int xcc_id) in gfx_v6_0_select_se_sh() argument
1297 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) in gfx_v6_0_select_se_sh()
1302 (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT); in gfx_v6_0_select_se_sh()
1303 else if (sh_num == 0xffffffff) in gfx_v6_0_select_se_sh()
1307 data |= (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT) | in gfx_v6_0_select_se_sh()
H A Dgfx_v9_4_2.c850 u32 sh_num, u32 instance) in gfx_v9_4_2_select_se_sh() argument
867 if (sh_num == 0xffffffff) in gfx_v9_4_2_select_se_sh()
871 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); in gfx_v9_4_2_select_se_sh()
H A Dgfx_v7_0.c1553 u32 se_num, u32 sh_num, u32 instance, in gfx_v7_0_select_se_sh() argument
1563 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) in gfx_v7_0_select_se_sh()
1568 (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT); in gfx_v7_0_select_se_sh()
1569 else if (sh_num == 0xffffffff) in gfx_v7_0_select_se_sh()
1573 data |= (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT) | in gfx_v7_0_select_se_sh()
H A Damdgpu.h545 u32 sh_num, u32 reg_offset, u32 *value);
H A Dgfx_v9_4_3.c524 u32 sh_num, u32 instance, int xcc_id) in gfx_v9_4_3_xcc_select_se_sh() argument
541 if (sh_num == 0xffffffff) in gfx_v9_4_3_xcc_select_se_sh()
545 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); in gfx_v9_4_3_xcc_select_se_sh()
H A Dgfx_v11_0.c119 u32 sh_num, u32 instance, int xcc_id);
1532 u32 sh_num, u32 instance, int xcc_id) in gfx_v11_0_select_se_sh() argument
1549 if (sh_num == 0xffffffff) in gfx_v11_0_select_se_sh()
1553 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num); in gfx_v11_0_select_se_sh()
H A Dgfx_v8_0.c3398 u32 se_num, u32 sh_num, u32 instance, in gfx_v8_0_select_se_sh() argument
3413 if (sh_num == 0xffffffff) in gfx_v8_0_select_se_sh()
3416 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); in gfx_v8_0_select_se_sh()
H A Dgfx_v9_0.c2223 void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, in gfx_v9_0_select_se_sh() argument
2238 if (sh_num == 0xffffffff) in gfx_v9_0_select_se_sh()
2241 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num); in gfx_v9_0_select_se_sh()
H A Dgfx_v10_0.c3477 u32 sh_num, u32 instance, int xcc_id);
4692 u32 sh_num, u32 instance, int xcc_id) in gfx_v10_0_select_se_sh() argument
4709 if (sh_num == 0xffffffff) in gfx_v10_0_select_se_sh()
4713 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num); in gfx_v10_0_select_se_sh()
/openbmc/linux/drivers/gpu/drm/radeon/
H A Dsi.c2947 u32 se_num, u32 sh_num) in si_select_se_sh() argument
2951 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) in si_select_se_sh()
2954 data |= SE_BROADCAST_WRITES | SH_INDEX(sh_num); in si_select_se_sh()
2955 else if (sh_num == 0xffffffff) in si_select_se_sh()
2958 data |= SH_INDEX(sh_num) | SE_INDEX(se_num); in si_select_se_sh()
H A Dcik.c3027 u32 se_num, u32 sh_num) in cik_select_se_sh() argument
3031 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) in cik_select_se_sh()
3034 data |= SE_BROADCAST_WRITES | SH_INDEX(sh_num); in cik_select_se_sh()
3035 else if (sh_num == 0xffffffff) in cik_select_se_sh()
3038 data |= SH_INDEX(sh_num) | SE_INDEX(se_num); in cik_select_se_sh()