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Searched refs:set_rate (Results 1 – 25 of 340) sorted by relevance

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/openbmc/linux/arch/arm/mach-omap1/
H A Dclock_data.c113 .set_rate = &omap1_set_sossi_rate,
121 .set_rate = omap1_clk_set_rate_ckctl_arm,
135 .set_rate = omap1_clk_set_rate_ckctl_arm,
205 .set_rate = omap1_clk_set_rate_ckctl_arm,
213 .set_rate = omap1_clk_set_rate_ckctl_arm,
224 .set_rate = &omap1_clk_set_rate_dsp_domain,
248 .set_rate = omap1_clk_set_rate_ckctl_arm,
340 .set_rate = omap1_clk_set_rate_ckctl_arm,
353 .set_rate = omap1_clk_set_rate_ckctl_arm,
372 .set_rate = &omap1_set_uart_rate,
[all …]
/openbmc/linux/drivers/clk/starfive/
H A Dclk-starfive-jh71x0.c236 .set_rate = jh71x0_clk_set_rate,
243 .set_rate = jh71x0_clk_frac_set_rate,
253 .set_rate = jh71x0_clk_set_rate,
279 .set_rate = jh71x0_clk_set_rate,
291 .set_rate = jh71x0_clk_set_rate,
/openbmc/u-boot/drivers/clk/rockchip/
H A Dclk_rk3368.c282 static ulong rk3368_ddr_set_clk(struct rk3368_cru *cru, ulong set_rate) in rk3368_ddr_set_clk() argument
292 switch (set_rate) { in rk3368_ddr_set_clk()
303 pr_err("Unsupported SDRAM frequency!,%ld\n", set_rate); in rk3368_ddr_set_clk()
307 return set_rate; in rk3368_ddr_set_clk()
312 static ulong rk3368_gmac_set_clk(struct rk3368_cru *cru, ulong set_rate) in rk3368_gmac_set_clk() argument
322 ret = set_rate; in rk3368_gmac_set_clk()
338 div = DIV_ROUND_UP(pll_rate, set_rate) - 1; in rk3368_gmac_set_clk()
589 .set_rate = rk3368_clk_set_rate,
H A Dclk_rk3399.c750 ulong clk_id, ulong set_rate) in rk3399_mmc_set_clk() argument
760 src_clk_div = DIV_ROUND_UP(GPLL_HZ / 2, set_rate); in rk3399_mmc_set_clk()
764 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, set_rate); in rk3399_mmc_set_clk()
788 src_clk_div = DIV_ROUND_UP(GPLL_HZ, set_rate); in rk3399_mmc_set_clk()
828 ulong set_rate) in rk3399_ddr_set_clk() argument
836 switch (set_rate) { in rk3399_ddr_set_clk()
858 pr_err("Unsupported SDRAM frequency!,%ld\n", set_rate); in rk3399_ddr_set_clk()
862 return set_rate; in rk3399_ddr_set_clk()
1087 .set_rate = rk3399_clk_set_rate,
1363 .set_rate = rk3399_pmuclk_set_rate,
H A Dclk_rk322x.c317 static int rk322x_ddr_set_clk(struct rk322x_cru *cru, unsigned int set_rate) in rk322x_ddr_set_clk() argument
322 switch (set_rate) { in rk322x_ddr_set_clk()
345 return set_rate; in rk322x_ddr_set_clk()
467 .set_rate = rk322x_clk_set_rate,
/openbmc/linux/drivers/clk/ti/
H A Ddpll.c29 .set_rate = &omap3_noncore_dpll_set_rate,
54 .set_rate = &omap3_noncore_dpll_set_rate,
67 .set_rate = &omap3_noncore_dpll_set_rate,
86 .set_rate = &omap2_reprogram_dpllcore,
108 .set_rate = &omap3_noncore_dpll_set_rate,
120 .set_rate = &omap3_dpll5_set_rate,
132 .set_rate = &omap3_dpll4_set_rate,
/openbmc/u-boot/drivers/clk/sifive/
H A Dfu540-prci.c187 int (*set_rate)(struct __prci_clock *pc, member
451 .set_rate = sifive_fu540_prci_wrpll_set_rate,
552 if (!pc->pd || !pc->ops->set_rate) in sifive_fu540_prci_set_rate()
555 err = pc->ops->set_rate(pc, rate, clk_get_rate(&pc->pd->parent)); in sifive_fu540_prci_set_rate()
587 .set_rate = sifive_fu540_prci_set_rate,
/openbmc/linux/drivers/clk/actions/
H A Dowl-composite.c169 .set_rate = owl_comp_div_set_rate,
186 .set_rate = owl_comp_fact_set_rate,
198 .set_rate = owl_comp_fix_fact_set_rate,
/openbmc/linux/drivers/sh/clk/
H A Dcpg.c182 .set_rate = sh_clk_div_set_rate,
188 .set_rate = sh_clk_div_set_rate,
315 .set_rate = sh_clk_div_set_rate,
367 .set_rate = sh_clk_div_set_rate,
447 .set_rate = fsidiv_set_rate,
H A Dcore.c490 if (likely(clk->ops && clk->ops->set_rate)) { in clk_set_rate()
491 ret = clk->ops->set_rate(clk, rate); in clk_set_rate()
583 if (likely(clkp->ops->set_rate)) in clks_core_resume()
584 clkp->ops->set_rate(clkp, rate); in clks_core_resume()
/openbmc/linux/drivers/clk/mvebu/
H A Dclk-corediv.c203 .set_rate = clk_corediv_set_rate,
219 .set_rate = clk_corediv_set_rate,
232 .set_rate = clk_corediv_set_rate,
244 .set_rate = clk_corediv_set_rate,
/openbmc/linux/drivers/clk/
H A Dclk-composite.c174 return rate_ops->set_rate(rate_hw, rate, parent_rate); in clk_composite_set_rate()
194 rate_ops->set_rate(rate_hw, rate, parent_rate); in clk_composite_set_rate_and_parent()
198 rate_ops->set_rate(rate_hw, rate, parent_rate); in clk_composite_set_rate_and_parent()
296 if (rate_ops->set_rate) { in __clk_hw_register_composite()
298 clk_composite_ops->set_rate = in __clk_hw_register_composite()
310 if (mux_ops->set_parent && rate_ops->set_rate) in __clk_hw_register_composite()
/openbmc/linux/drivers/clk/mxs/
H A Dclk-div.c57 ret = div->ops->set_rate(&div->divider.hw, rate, parent_rate); in clk_div_set_rate()
67 .set_rate = clk_div_set_rate,
/openbmc/linux/arch/sh/kernel/cpu/sh4/
H A Dclock-sh4-202.c81 if (clk->ops->set_rate(clk, clk->parent->rate / divisor) == 0) in shoc_clk_init()
133 .set_rate = shoc_clk_set_rate,
/openbmc/linux/drivers/clk/tegra/
H A Dclk-periph.c75 return div_ops->set_rate(div_hw, rate, parent_rate); in clk_periph_set_rate()
140 .set_rate = clk_periph_set_rate,
164 .set_rate = clk_periph_set_rate,
H A Dclk-tegra-super-cclk.c46 return tegra_clk_super_ops.set_rate(hw, rate, parent_rate); in cclk_super_set_rate()
121 .set_rate = cclk_super_set_rate,
/openbmc/linux/include/linux/phy/
H A Dphy-dp.h73 u8 set_rate : 1; member
/openbmc/linux/drivers/clk/qcom/
H A Dclk-alpha-pll.c1062 .set_rate = clk_alpha_pll_set_rate,
1072 .set_rate = alpha_pll_huayra_set_rate,
1082 .set_rate = clk_alpha_pll_hwfsm_set_rate,
1177 .set_rate = clk_alpha_pll_postdiv_set_rate,
1422 .set_rate = alpha_pll_fabia_set_rate,
1517 .set_rate = clk_trion_pll_postdiv_set_rate,
1563 .set_rate = clk_alpha_pll_postdiv_fabia_set_rate,
1715 .set_rate = alpha_pll_trion_set_rate,
1726 .set_rate = alpha_pll_trion_set_rate,
1733 .set_rate = clk_alpha_pll_postdiv_fabia_set_rate,
[all …]
H A Dclk-rcg2.c488 .set_rate = clk_rcg2_set_rate,
501 .set_rate = clk_rcg2_set_floor_rate,
636 .set_rate = clk_edp_pixel_set_rate,
694 .set_rate = clk_byte_set_rate,
764 .set_rate = clk_byte2_set_rate,
855 .set_rate = clk_pixel_set_rate,
969 .set_rate = clk_gfx3d_set_rate,
1206 .set_rate = clk_rcg2_shared_set_rate,
1218 .set_rate = clk_rcg2_shared_set_floor_rate,
1248 .set_rate = clk_rcg2_shared_set_rate,
[all …]
H A Dclk-rcg.c828 .set_rate = clk_rcg_set_rate,
839 .set_rate = clk_rcg_set_floor_rate,
850 .set_rate = clk_rcg_bypass_set_rate,
861 .set_rate = clk_rcg_bypass2_set_rate,
873 .set_rate = clk_rcg_pixel_set_rate,
885 .set_rate = clk_rcg_esc_set_rate,
897 .set_rate = clk_rcg_lcc_set_rate,
909 .set_rate = clk_dyn_rcg_set_rate,
/openbmc/linux/drivers/clk/samsung/
H A Dclk-pll.c297 .set_rate = samsung_pll35xx_set_rate,
408 .set_rate = samsung_pll36xx_set_rate,
492 .set_rate = samsung_pll0822x_set_rate,
588 .set_rate = samsung_pll0831x_set_rate,
713 .set_rate = samsung_pll45xx_set_rate,
858 .set_rate = samsung_pll46xx_set_rate,
1071 .set_rate = samsung_pll2550xx_set_rate,
1163 .set_rate = samsung_pll2650x_set_rate,
1253 .set_rate = samsung_pll2650xx_set_rate,
/openbmc/linux/drivers/clk/st/
H A Dclk-flexgen.c185 clk_divider_ops.set_rate(pdiv_hw, parent_rate, parent_rate); in flexgen_set_rate()
186 ret = clk_divider_ops.set_rate(fdiv_hw, rate, rate * div); in flexgen_set_rate()
188 clk_divider_ops.set_rate(fdiv_hw, parent_rate, parent_rate); in flexgen_set_rate()
189 ret = clk_divider_ops.set_rate(pdiv_hw, rate, rate * div); in flexgen_set_rate()
203 .set_rate = flexgen_set_rate,
/openbmc/linux/drivers/clk/imx/
H A Dclk-pllv3.c156 .set_rate = clk_pllv3_set_rate,
211 .set_rate = clk_pllv3_sys_set_rate,
300 .set_rate = clk_pllv3_av_set_rate,
393 .set_rate = clk_pllv3_vf610_set_rate,
/openbmc/linux/drivers/clk/ux500/
H A Dclk-prcmu.c161 .set_rate = clk_prcmu_set_rate,
173 .set_rate = clk_prcmu_set_rate,
191 .set_rate = clk_prcmu_set_rate,
/openbmc/u-boot/include/
H A Dclk-uclass.h78 ulong (*set_rate)(struct clk *clk, ulong rate); member

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