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Searched refs:set_bits (Results 1 – 25 of 51) sorted by relevance

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/openbmc/linux/tools/perf/bench/
H A Dfind-bit-bench.c63 unsigned int set_bits, skip; in do_for_each_set_bit() local
68 for (set_bits = 1; set_bits <= num_bits; set_bits <<= 1) { in do_for_each_set_bit()
70 skip = num_bits / set_bits; in do_for_each_set_bit()
85 assert(old + (inner_iterations * set_bits) == accumulator); in do_for_each_set_bit()
101 assert(old + (inner_iterations * set_bits) == accumulator); in do_for_each_set_bit()
108 inner_iterations, set_bits, num_bits); in do_for_each_set_bit()
/openbmc/u-boot/drivers/led/
H A Dled_bcm6358.c120 u32 set_bits = 0; in bcm6358_led_probe() local
127 set_bits |= LED_CTRL_POL_MASK; in bcm6358_led_probe()
132 set_bits |= LED_CTRL_CLK_8; in bcm6358_led_probe()
135 set_bits |= LED_CTRL_CLK_4; in bcm6358_led_probe()
138 set_bits |= LED_CTRL_CLK_2; in bcm6358_led_probe()
141 set_bits |= LED_CTRL_CLK_1; in bcm6358_led_probe()
148 set_bits); in bcm6358_led_probe()
H A Dled_bcm6328.c154 u32 set_bits = 0; in bcm6328_led_probe() local
161 set_bits |= LED_INIT_SLEDEN_MASK; in bcm6328_led_probe()
163 set_bits |= LED_INIT_SLEDMUX_MASK; in bcm6328_led_probe()
165 set_bits |= LED_INIT_SLEDCLKNPOL_MASK; in bcm6328_led_probe()
167 set_bits |= LED_INIT_SLEDDATANPOL_MASK; in bcm6328_led_probe()
169 set_bits |= LED_INIT_SLEDSHIFTDIR_MASK; in bcm6328_led_probe()
171 clrsetbits_be32(regs + LED_INIT_REG, ~0, set_bits); in bcm6328_led_probe()
/openbmc/linux/drivers/media/platform/ti/omap3isp/
H A Disp.h331 u32 reg, u32 set_bits) in isp_reg_set() argument
335 isp_reg_writel(isp, v | set_bits, mmio_range, reg); in isp_reg_set()
350 u32 reg, u32 clr_bits, u32 set_bits) in isp_reg_clr_set() argument
354 isp_reg_writel(isp, (v & ~clr_bits) | set_bits, mmio_range, reg); in isp_reg_clr_set()
/openbmc/qemu/target/s390x/
H A Dgen-features.c890 static void set_bits(uint64_t list[], BitSpec bits) in set_bits() function
920 set_bits(base_feat, CpuFeatDef[i].base_bits); in print_feature_defs()
922 set_bits(default_feat, CpuFeatDef[i].base_bits); in print_feature_defs()
923 set_bits(default_feat, CpuFeatDef[i].default_bits); in print_feature_defs()
925 set_bits(full_feat, CpuFeatDef[i].base_bits); in print_feature_defs()
926 set_bits(full_feat, CpuFeatDef[i].full_bits); in print_feature_defs()
967 set_bits(feat, QemuFeatDef[i].bits); in print_qemu_feature_defs()
990 set_bits(feat, FeatGroupDef[i].bits); in print_feature_group_defs()
/openbmc/linux/drivers/gpu/drm/sprd/
H A Dsprd_dpu.h75 dpu_reg_set(struct dpu_context *ctx, u32 offset, u32 set_bits) in dpu_reg_set() argument
79 writel(bits | set_bits, ctx->base + offset); in dpu_reg_set()
/openbmc/linux/fs/fscache/
H A Dio.c206 bool set_bits; member
239 wreq->set_bits); in fscache_wreq_done()
271 wreq->set_bits = cond; in __fscache_write_to_cache()
/openbmc/linux/drivers/tty/serial/
H A Dip22zilog.c546 unsigned char set_bits, clear_bits; in ip22zilog_set_mctrl() local
548 set_bits = clear_bits = 0; in ip22zilog_set_mctrl()
551 set_bits |= RTS; in ip22zilog_set_mctrl()
555 set_bits |= DTR; in ip22zilog_set_mctrl()
560 up->curregs[R5] |= set_bits; in ip22zilog_set_mctrl()
657 unsigned char set_bits, clear_bits, new_reg; in ip22zilog_break_ctl() local
660 set_bits = clear_bits = 0; in ip22zilog_break_ctl()
663 set_bits |= SND_BRK; in ip22zilog_break_ctl()
669 new_reg = (up->curregs[R5] | set_bits) & ~clear_bits; in ip22zilog_break_ctl()
H A Dpmac_zilog.c516 unsigned char set_bits, clear_bits; in pmz_set_mctrl() local
525 set_bits = clear_bits = 0; in pmz_set_mctrl()
529 set_bits |= RTS; in pmz_set_mctrl()
534 set_bits |= DTR; in pmz_set_mctrl()
539 uap->curregs[R5] |= set_bits; in pmz_set_mctrl()
544 set_bits, clear_bits, uap->curregs[R5]); in pmz_set_mctrl()
664 unsigned char set_bits, clear_bits, new_reg; in pmz_break_ctl() local
667 set_bits = clear_bits = 0; in pmz_break_ctl()
670 set_bits |= SND_BRK; in pmz_break_ctl()
676 new_reg = (uap->curregs[R5] | set_bits) & ~clear_bits; in pmz_break_ctl()
H A Dsunzilog.c646 unsigned char set_bits, clear_bits; in sunzilog_set_mctrl() local
648 set_bits = clear_bits = 0; in sunzilog_set_mctrl()
651 set_bits |= RTS; in sunzilog_set_mctrl()
655 set_bits |= DTR; in sunzilog_set_mctrl()
660 up->curregs[R5] |= set_bits; in sunzilog_set_mctrl()
757 unsigned char set_bits, clear_bits, new_reg; in sunzilog_break_ctl() local
760 set_bits = clear_bits = 0; in sunzilog_break_ctl()
763 set_bits |= SND_BRK; in sunzilog_break_ctl()
769 new_reg = (up->curregs[R5] | set_bits) & ~clear_bits; in sunzilog_break_ctl()
/openbmc/linux/arch/arm/mach-omap2/
H A Domap-secure.c190 u32 rx51_secure_update_aux_cr(u32 set_bits, u32 clear_bits) in rx51_secure_update_aux_cr() argument
197 acr |= set_bits; in rx51_secure_update_aux_cr()
H A Domap-secure.h77 extern u32 rx51_secure_update_aux_cr(u32 set_bits, u32 clear_bits);
/openbmc/u-boot/drivers/sound/
H A Dhda_codec.c125 static int set_bits(void *port, u32 mask, u32 val) in set_bits() function
153 if (set_bits(&regs->gctl, 1, 1)) in hda_codec_detect()
168 set_bits(&regs->gctl, 1, 0); in hda_codec_detect()
/openbmc/linux/arch/powerpc/include/asm/
H A Dbitops.h82 DEFINE_BITOP(set_bits, or, "")
131 set_bits(BIT_MASK(nr), addr + BIT_WORD(nr)); in DEFINE_CLROP()
/openbmc/u-boot/arch/arm/mach-omap2/omap3/
H A Dboard.c402 static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits) in omap3_update_aux_cr() argument
409 acr |= set_bits; in omap3_update_aux_cr()
/openbmc/linux/drivers/hwmon/
H A Dgl518sm.c299 #define set_bits(type, suffix, value, reg, mask, shift) \ macro
322 set_bits(type, suffix, value, reg, 0x00ff, 0)
324 set_bits(type, suffix, value, reg, 0xff00, 8)
328 set_bits(BOOL, fan_auto1, fan_auto1, GL518_REG_MISC, 0x08, 3);
337 set_bits(BOOL, beep_enable, beep_enable, GL518_REG_CONF, 0x04, 2);
/openbmc/linux/drivers/gpu/drm/i915/gvt/
H A Dinterrupt.c331 u32 set_bits = 0; in update_upstream_irq() local
355 set_bits |= (1 << bit); in update_upstream_irq()
367 vgpu_vreg(vgpu, isr) |= set_bits; in update_upstream_irq()
374 vgpu_vreg(vgpu, iir) |= (set_bits & ~vgpu_vreg(vgpu, imr)); in update_upstream_irq()
/openbmc/linux/include/trace/events/
H A Dbtrfs.h2092 u64 start, u64 len, unsigned set_bits),
2094 TP_ARGS(tree, start, len, set_bits),
2102 __field( unsigned, set_bits)
2118 __entry->set_bits = set_bits;
2125 __print_flags(__entry->set_bits, "|", EXTENT_FLAGS))
2168 u64 start, u64 len, unsigned set_bits, unsigned clear_bits),
2170 TP_ARGS(tree, start, len, set_bits, clear_bits),
2178 __field( unsigned, set_bits)
2195 __entry->set_bits = set_bits;
2203 __print_flags(__entry->set_bits , "|", EXTENT_FLAGS),
/openbmc/linux/drivers/gpio/
H A Dgpio-thunderx.c276 u64 set_bits, clear_bits; in thunderx_gpio_set_multiple() local
280 set_bits = bits[bank] & mask[bank]; in thunderx_gpio_set_multiple()
282 writeq(set_bits, txgpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_TX_SET); in thunderx_gpio_set_multiple()
/openbmc/u-boot/arch/arm/include/asm/arch-omap5/
H A Domap.h256 void clrset_spare_register(u8 spare_type, u32 clear_bits, u32 set_bits);
/openbmc/linux/arch/powerpc/kernel/
H A Dsyscall.c88 set_bits(_TIF_RESTOREALL, &current_thread_info()->flags); in system_call_exception()
/openbmc/linux/arch/arm/mach-ep93xx/
H A Dsoc.h200 void ep93xx_devcfg_set_clear(unsigned int set_bits, unsigned int clear_bits);
/openbmc/u-boot/board/nokia/rx51/
H A Drx51.c361 static void omap3_update_aux_cr_secure_rx51(u32 set_bits, u32 clear_bits) in omap3_update_aux_cr_secure_rx51() argument
368 acr |= set_bits; in omap3_update_aux_cr_secure_rx51()
/openbmc/linux/drivers/net/ethernet/chelsio/cxgb3/
H A Dael1002.c81 unsigned short set_bits; member
91 rv->set_bits); in set_phy_regs()
95 rv->set_bits); in set_phy_regs()
/openbmc/linux/drivers/net/ethernet/smsc/
H A Dsmc91c92_cs.c262 #define set_bits(v, p) outw(inw(p)|(v), (p)) macro
702 set_bits(0x300, link->resource[0]->start + OSITECH_AUI_PWR); in osi_setup()
704 set_bits(0x300, link->resource[0]->start + OSITECH_RESET_ISR); in osi_setup()
736 set_bits(0x0300, dev->base_addr-0x10+OSITECH_AUI_PWR); in smc91c92_resume()
737 set_bits(0x0300, dev->base_addr-0x10+OSITECH_RESET_ISR); in smc91c92_resume()
1442 set_bits(0x0300, ioaddr-0x10+OSITECH_RESET_ISR); in smc_interrupt()
1627 set_bits(OSI_AUI_PWR, ioaddr - 0x10 + OSITECH_AUI_PWR); in smc_set_xcvr()

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