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Searched refs:rk_clrsetreg (Results 1 – 25 of 32) sorted by relevance

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/openbmc/u-boot/arch/arm/mach-rockchip/rk3368/
H A Drk3368.c71 rk_clrsetreg(&grf->soc_con14, MCU_SRAM_BASE_BIT31_BIT28_MASK, in mcu_init()
73 rk_clrsetreg(&grf->soc_con11, MCU_SRAM_BASE_BIT27_BIT12_MASK, in mcu_init()
75 rk_clrsetreg(&grf->soc_con14, MCU_EXSRAM_BASE_BIT31_BIT28_MASK, in mcu_init()
77 rk_clrsetreg(&grf->soc_con12, MCU_EXSRAM_BASE_BIT27_BIT12_MASK, in mcu_init()
79 rk_clrsetreg(&grf->soc_con14, MCU_EXPERI_BASE_BIT31_BIT28_MASK, in mcu_init()
81 rk_clrsetreg(&grf->soc_con13, MCU_EXPERI_BASE_BIT27_BIT12_MASK, in mcu_init()
84 rk_clrsetreg(&cru->clksel_con[12], MCU_PLL_SEL_MASK | MCU_CLK_DIV_MASK, in mcu_init()
/openbmc/u-boot/drivers/clk/rockchip/
H A Dclk_rv1108.c85 rk_clrsetreg(&pll->con3, WORK_MODE_MASK, in rkclk_set_pll()
93 rk_clrsetreg(&pll->con0, FBDIV_MASK, div->fbdiv << FBDIV_SHIFT); in rkclk_set_pll()
94 rk_clrsetreg(&pll->con1, POSTDIV1_MASK | POSTDIV2_MASK | REFDIV_MASK, in rkclk_set_pll()
98 rk_clrsetreg(&pll->con2, FRACDIV_MASK, in rkclk_set_pll()
111 rk_clrsetreg(&pll->con3, WORK_MODE_MASK, in rkclk_set_pll()
160 rk_clrsetreg(&cru->clksel_con[24], MAC_CLK_DIV_MASK, in rv1108_mac_set_clk()
181 rk_clrsetreg(&cru->clksel_con[27], SFC_CLK_DIV_MASK, in rv1108_sfc_set_clk()
207 rk_clrsetreg(&cru->clksel_con[22], in rv1108_saradc_set_clk()
232 rk_clrsetreg(&cru->clksel_con[28], in rv1108_aclk_vio1_set_clk()
258 rk_clrsetreg(&cru->clksel_con[28], in rv1108_aclk_vio0_set_clk()
[all …]
H A Dclk_rk3288.c162 rk_clrsetreg(&pll->con0, CLKR_MASK | PLL_OD_MASK, in rkclk_set_pll()
164 rk_clrsetreg(&pll->con1, CLKF_MASK, div->nf - 1); in rkclk_set_pll()
165 rk_clrsetreg(&pll->con2, PLL_BWADJ_MASK, (div->nf >> 1) - 1); in rkclk_set_pll()
205 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK, in rkclk_configure_ddr()
215 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK, in rkclk_configure_ddr()
325 rk_clrsetreg(&cru->cru_clksel_con[21], MAC_DIV_CON_MASK, in rockchip_mac_set_clk()
347 rk_clrsetreg(&cru->cru_mode_con, NPLL_MODE_MASK, in rockchip_vop_set_clk()
358 rk_clrsetreg(&cru->cru_mode_con, NPLL_MODE_MASK, in rockchip_vop_set_clk()
364 rk_clrsetreg(&cru->cru_clksel_con[27], 0xff << 8 | 3 << 0, in rockchip_vop_set_clk()
368 rk_clrsetreg(&cru->cru_clksel_con[29], 0xff << 8 | 3 << 6, in rockchip_vop_set_clk()
[all …]
H A Dclk_rk322x.c62 rk_clrsetreg(&pll->con0, in rkclk_set_pll()
65 rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK, in rkclk_set_pll()
86 rk_clrsetreg(&cru->cru_mode_con, in rkclk_init()
106 rk_clrsetreg(&cru->cru_clksel_con[0], in rkclk_init()
111 rk_clrsetreg(&cru->cru_clksel_con[1], in rkclk_init()
129 rk_clrsetreg(&cru->cru_clksel_con[0], in rkclk_init()
134 rk_clrsetreg(&cru->cru_clksel_con[1], in rkclk_init()
154 rk_clrsetreg(&cru->cru_clksel_con[10], in rkclk_init()
163 rk_clrsetreg(&cru->cru_mode_con, in rkclk_init()
263 rk_clrsetreg(&cru->cru_clksel_con[5], CLK_MAC_DIV_MASK, in rk322x_mac_set_clk()
[all …]
H A Dclk_rk3188.c103 rk_clrsetreg(&pll->con0, in rkclk_set_pll()
106 rk_clrsetreg(&pll->con1, CLKF_MASK, div->nf - 1); in rkclk_set_pll()
109 rk_clrsetreg(&pll->con2, PLL_BWADJ_MASK, (div->nf >> 1) - 1); in rkclk_set_pll()
149 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK << DPLL_MODE_SHIFT, in rkclk_configure_ddr()
159 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK << DPLL_MODE_SHIFT, in rkclk_configure_ddr()
198 rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK << APLL_MODE_SHIFT, in rkclk_configure_cpu()
208 rk_clrsetreg(&cru->cru_clksel_con[0], in rkclk_configure_cpu()
213 rk_clrsetreg(&cru->cru_clksel_con[1], in rkclk_configure_cpu()
218 rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK << APLL_MODE_SHIFT, in rkclk_configure_cpu()
300 rk_clrsetreg(&cru->cru_clksel_con[12], in rockchip_mmc_set_clk()
[all …]
H A Dclk_rk3399.c332 rk_clrsetreg(&pll_con[3], PLL_MODE_MASK, in rkclk_set_pll()
336 rk_clrsetreg(&pll_con[3], PLL_DSMPD_MASK, in rkclk_set_pll()
339 rk_clrsetreg(&pll_con[0], PLL_FBDIV_MASK, in rkclk_set_pll()
341 rk_clrsetreg(&pll_con[1], in rkclk_set_pll()
353 rk_clrsetreg(&pll_con[3], PLL_MODE_MASK, in rkclk_set_pll()
443 rk_clrsetreg(&cru->clksel_con[0], in rk3399_configure_cpu_l()
450 rk_clrsetreg(&cru->clksel_con[1], in rk3399_configure_cpu_l()
478 rk_clrsetreg(&cru->clksel_con[2], in rk3399_configure_cpu_b()
485 rk_clrsetreg(&cru->clksel_con[3], in rk3399_configure_cpu_b()
562 rk_clrsetreg(&cru->clksel_con[61], I2C_CLK_REG_MASK(1), in rk3399_i2c_set_clk()
[all …]
H A Dclk_rk3328.c256 rk_clrsetreg(&cru->mode_con, mode_mask, PLL_MODE_SLOW << mode_shift); in rkclk_set_pll()
259 rk_clrsetreg(&pll_con[1], PLL_DSMPD_MASK, in rkclk_set_pll()
262 rk_clrsetreg(&pll_con[0], in rkclk_set_pll()
266 rk_clrsetreg(&pll_con[1], in rkclk_set_pll()
276 rk_clrsetreg(&cru->mode_con, mode_mask, PLL_MODE_NORM << mode_shift); in rkclk_set_pll()
294 rk_clrsetreg(&cru->clksel_con[28], in rkclk_init()
298 rk_clrsetreg(&cru->clksel_con[29], in rkclk_init()
317 rk_clrsetreg(&cru->clksel_con[0], in rk3328_configure_cpu()
322 rk_clrsetreg(&cru->clksel_con[1], in rk3328_configure_cpu()
367 rk_clrsetreg(&cru->clksel_con[34], in rk3328_i2c_set_clk()
[all …]
H A Dclk_rk3128.c59 rk_clrsetreg(&pll->con0, in rkclk_set_pll()
62 rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK, in rkclk_set_pll()
147 rk_clrsetreg(&cru->cru_mode_con, in rkclk_init()
167 rk_clrsetreg(&cru->cru_clksel_con[0], in rkclk_init()
172 rk_clrsetreg(&cru->cru_clksel_con[1], in rkclk_init()
190 rk_clrsetreg(&cru->cru_clksel_con[0], in rkclk_init()
195 rk_clrsetreg(&cru->cru_clksel_con[1], in rkclk_init()
215 rk_clrsetreg(&cru->cru_clksel_con[10], in rkclk_init()
224 rk_clrsetreg(&cru->cru_mode_con, in rkclk_init()
231 rk_clrsetreg(&cru->cru_clksel_con[2], in rkclk_init()
[all …]
H A Dclk_rk3036.c64 rk_clrsetreg(&pll->con0, in rkclk_set_pll()
67 rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK, in rkclk_set_pll()
85 rk_clrsetreg(&cru->cru_mode_con, in rkclk_init()
105 rk_clrsetreg(&cru->cru_clksel_con[0], in rkclk_init()
110 rk_clrsetreg(&cru->cru_clksel_con[1], in rkclk_init()
128 rk_clrsetreg(&cru->cru_clksel_con[0], in rkclk_init()
133 rk_clrsetreg(&cru->cru_clksel_con[1], in rkclk_init()
153 rk_clrsetreg(&cru->cru_clksel_con[10], in rkclk_init()
162 rk_clrsetreg(&cru->cru_mode_con, in rkclk_init()
260 rk_clrsetreg(&cru->cru_clksel_con[12], in rockchip_mmc_set_clk()
[all …]
H A Dclk_rk3368.c100 rk_clrsetreg(&pll->con3, PLL_MODE_MASK | PLL_RESET_MASK, in rkclk_set_pll()
103 rk_clrsetreg(&pll->con0, PLL_NR_MASK | PLL_OD_MASK, in rkclk_set_pll()
122 rk_clrsetreg(&pll->con3, PLL_MODE_MASK, in rkclk_set_pll()
273 rk_clrsetreg(&cru->clksel_con[con_id], in rk3368_mmc_set_clk()
340 rk_clrsetreg(&cru->clksel_con[43], GMAC_DIV_CON_MASK, in rk3368_gmac_set_clk()
418 rk_clrsetreg(&cru->clksel_con[spiclk->reg], in rk3368_spi_set_clk()
445 rk_clrsetreg(&cru->clksel_con[25], in rk3368_saradc_set_clk()
/openbmc/u-boot/drivers/net/
H A Dgmac_rockchip.c103 rk_clrsetreg(&grf->mac_con[1], RK3228_GMAC_CLK_SEL_MASK, clk); in rk3228_gmac_fix_mac_speed()
129 rk_clrsetreg(&grf->soc_con1, RK3288_GMAC_CLK_SEL_MASK, clk); in rk3288_gmac_fix_mac_speed()
162 rk_clrsetreg(&grf->mac_con[1], RK3328_GMAC_CLK_SEL_MASK, clk); in rk3328_gmac_fix_mac_speed()
194 rk_clrsetreg(&grf->soc_con15, RK3368_GMAC_CLK_SEL_MASK, clk); in rk3368_gmac_fix_mac_speed()
220 rk_clrsetreg(&grf->soc_con5, RK3399_GMAC_CLK_SEL_MASK, clk); in rk3399_gmac_fix_mac_speed()
253 rk_clrsetreg(&grf->gmac_con0, in rv1108_set_rmii_speed()
288 rk_clrsetreg(&grf->mac_con[1], in rk3228_gmac_set_to_rgmii()
296 rk_clrsetreg(&grf->mac_con[0], in rk3228_gmac_set_to_rgmii()
308 rk_clrsetreg(&grf->soc_con1, in rk3288_gmac_set_to_rgmii()
312 rk_clrsetreg(&grf->soc_con3, in rk3288_gmac_set_to_rgmii()
[all …]
/openbmc/u-boot/arch/arm/mach-rockchip/
H A Drk3399-board-spl.c143 rk_clrsetreg(&grf->gpio2c_iomux, in board_debug_uart_init()
146 rk_clrsetreg(&grf->gpio2c_iomux, in board_debug_uart_init()
165 rk_clrsetreg(&grf->gpio4c_iomux, in board_debug_uart_init()
168 rk_clrsetreg(&grf->gpio4c_iomux, in board_debug_uart_init()
172 rk_clrsetreg(&grf->soc_con7, in board_debug_uart_init()
231 rk_clrsetreg(&sgrf->ddr_rgn_con[16], 0x1ff, 0); in board_init_f()
H A Drk3188-board-spl.c114 rk_clrsetreg(&grf->gpio1b_iomux, in board_debug_uart_init()
141 rk_clrsetreg(&grf->uoc0_con[0], in board_init_f()
145 rk_clrsetreg(&grf->uoc0_con[2], in board_init_f()
147 rk_clrsetreg(&grf->uoc0_con[3], in board_init_f()
154 rk_clrsetreg(&grf->uoc0_con[0], in board_init_f()
H A Drk322x-board.c55 rk_clrsetreg(&grf->gpio1b_iomux, in board_init()
60 rk_clrsetreg(&grf->con_iomux, in board_init()
68 rk_clrsetreg(&grf->macphy_con[0], in board_init()
H A Drk322x-board-spl.c52 rk_clrsetreg(&grf->gpio1b_iomux, in board_debug_uart_init()
57 rk_clrsetreg(&grf->con_iomux, in board_debug_uart_init()
H A Drk3368-board-tpl.c104 rk_clrsetreg(&grf->gpio2d_iomux, in board_debug_uart_init()
106 rk_clrsetreg(&grf->gpio2d_iomux, in board_debug_uart_init()
H A Drk3036-board-spl.c29 rk_clrsetreg(&grf->gpio1c_iomux, in board_init_f()
H A Drk3188-board.c35 rk_clrsetreg(&grf->soc_con0, in board_late_init()
H A Drk3288-board-tpl.c31 rk_clrsetreg(&grf->gpio7ch_iomux, GPIO7C7_MASK << GPIO7C7_SHIFT | in board_init_f()
/openbmc/u-boot/drivers/video/rockchip/
H A Drk3288_mipi.c38 rk_clrsetreg(&grf->soc_con6, RK3288_DSI0_LCDC_SEL_MASK, in rk_mipi_dsi_source_select()
43 rk_clrsetreg(&grf->soc_con6, RK3288_DSI0_LCDC_SEL_MASK, in rk_mipi_dsi_source_select()
64 rk_clrsetreg(&grf->soc_con8, RK3288_DPHY_TX0_RXMODE_MASK, val); in rk_mipi_dphy_mode_set()
69 rk_clrsetreg(&grf->soc_con8, in rk_mipi_dphy_mode_set()
75 rk_clrsetreg(&grf->soc_con8, in rk_mipi_dphy_mode_set()
H A Drk3399_mipi.c36 rk_clrsetreg(&grf->soc_con20, GRF_DSI0_VOP_SEL_MASK, in rk_mipi_dsi_source_select()
40 rk_clrsetreg(&grf->soc_con20, GRF_DSI0_VOP_SEL_MASK, in rk_mipi_dsi_source_select()
60 rk_clrsetreg(&grf->soc_con22, GRF_DPHY_TX0_RXMODE_MASK, val); in rk_mipi_dphy_mode_set()
64 rk_clrsetreg(&grf->soc_con22, GRF_DPHY_TX0_TXSTOPMODE_MASK, val); in rk_mipi_dphy_mode_set()
68 rk_clrsetreg(&grf->soc_con22, GRF_DPHY_TX0_TURNREQUEST_MASK, val); in rk_mipi_dphy_mode_set()
/openbmc/u-boot/arch/arm/mach-rockchip/rk3036/
H A Dsdram_rk3036.c332 rk_clrsetreg(&priv->cru->cru_mode_con, DPLL_MODE_MASK, in rkdclk_init()
338 rk_clrsetreg(&pll->con0, in rkdclk_init()
342 rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK, in rkdclk_init()
351 rk_clrsetreg(&priv->cru->cru_mode_con, DPLL_MODE_MASK, in rkdclk_init()
370 rk_clrsetreg(&priv->cru->cru_softrst_con[5], 1 << DDRCTRL_PSRST_SHIFT | in phy_pctrl_reset()
/openbmc/u-boot/drivers/ram/rockchip/
H A Dsdram_rk3288.c102 rk_clrsetreg(&cru->cru_softrst_con[10], in ddr_reset()
115 rk_clrsetreg(&cru->cru_softrst_con[10], in ddr_phy_ctl_reset()
204 rk_clrsetreg(&grf->soc_con0, in ddr_set_enable()
217 rk_clrsetreg(&grf->soc_con0, mask, val); in ddr_set_ddr3_mode()
231 rk_clrsetreg(&grf->soc_con2, mask, in ddr_set_en_bst_odt()
614 rk_clrsetreg(&dram->sgrf->soc_con2, 0x1f, sdram_params->base.stride); in dram_all_config()
811 rk_clrsetreg(&dram->sgrf->soc_con2, 0x1f, 0x17); in sdram_init()
813 rk_clrsetreg(&dram->sgrf->soc_con2, 0x1f, 0x1a); in sdram_init()
/openbmc/u-boot/arch/arm/include/asm/arch-rockchip/
H A Dhardware.h15 #define rk_clrsetreg(addr, clr, set) \ macro
/openbmc/u-boot/board/rockchip/evb_rv1108/
H A Devb_rv1108.c41 rk_clrsetreg(&grf->gpio2d_iomux, in mach_cpu_init()

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