| /openbmc/u-boot/arch/arm/mach-rockchip/ |
| H A D | rk3368-board-tpl.c | 62 rk_clrreg(sgrf_soc_con_addr(8), SGRF_SOC_CON_SEC); in sgrf_init()
63 rk_clrreg(sgrf_soc_con_addr(9), SGRF_SOC_CON_SEC); in sgrf_init()
64 rk_clrreg(sgrf_soc_con_addr(10), SGRF_SOC_CON_SEC); in sgrf_init()
78 rk_clrreg(&cru->softrst_con[1], DMA1_SRST_REQ); in sgrf_init()
79 rk_clrreg(&cru->softrst_con[4], DMA2_SRST_REQ); in sgrf_init()
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| H A D | rk3399-board-spl.c | 232 rk_clrreg(&sgrf->slv_secure_con4, 0x2000); in board_init_f()
236 rk_clrreg(&grf->emmccore_con[11], 0x0ff); in board_init_f()
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| H A D | rk3288-board.c | 82 rk_clrreg(&cru->cru_glb_rst_st, GLB_RST_ST_MASK); in rk3288_detect_reset_reason()
356 rk_clrreg(GRF_SOC_CON0, 1 << 12); in board_early_init_f()
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| H A D | rk322x-board-spl.c | 94 rk_clrreg(SGRF_DDR_CON0, 0x4000); in board_init_f()
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| /openbmc/u-boot/arch/arm/include/asm/arch-rockchip/ |
| H A D | hardware.h | 17 #define rk_clrreg(addr, clr) writel((clr) << 16, addr) macro
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| /openbmc/u-boot/arch/arm/mach-rockchip/rk3399/ |
| H A D | rk3399.c | 53 rk_clrreg(GRF_EMMCCORE_CON11, 0x0ff); in arch_cpu_init()
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| /openbmc/u-boot/board/rockchip/evb_rv1108/ |
| H A D | evb_rv1108.c | 45 rk_clrreg(&grf->gpio3c_iomux, GPIO3C3_MASK | GPIO3C2_MASK); in mach_cpu_init()
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| /openbmc/u-boot/board/elgin/elgin_rv1108/ |
| H A D | elgin_rv1108.c | 46 rk_clrreg(&grf->gpio3c_iomux, GPIO3C3_MASK | GPIO3C2_MASK); in mach_cpu_init()
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| /openbmc/u-boot/arch/arm/mach-rockchip/rk3368/ |
| H A D | rk3368.c | 89 rk_clrreg(&cru->softrst_con[1], MCU_PO_SRST_MASK | MCU_SYS_SRST_MASK); in mcu_init()
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| /openbmc/u-boot/drivers/clk/rockchip/ |
| H A D | clk_rk3288.c | 170 rk_clrreg(&pll->con3, 1 << PLL_RESET_SHIFT); in rkclk_set_pll()
834 rk_clrreg(&cru->cru_clksel_con[6], 1 << 15); in rk3288_clk_set_rate()
862 rk_clrreg(&cru->cru_clkgate_con[16], 1 << 9); in rk3288_clk_set_rate()
867 rk_clrreg(&cru->cru_clkgate_con[7], 1 << 9); in rk3288_clk_set_rate()
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| H A D | clk_rk3368.c | 116 rk_clrreg(&pll->con3, PLL_RESET_MASK); in rkclk_set_pll()
535 rk_clrreg(&cru->clksel_con[43], GMAC_MUX_SEL_EXTCLK); in rk3368_gmac_set_parent()
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| H A D | clk_rk3328.c | 668 rk_clrreg(&grf->mac_con[1], BIT(10)); in rk3328_gmac2io_set_parent()
705 rk_clrreg(&grf->soc_con[4], BIT(14)); in rk3328_gmac2io_ext_set_parent()
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| H A D | clk_rk322x.c | 70 rk_clrreg(&pll->con1, 1 << PLL_PD_SHIFT); in rkclk_set_pll()
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| H A D | clk_rk3188.c | 114 rk_clrreg(&pll->con3, 1 << PLL_RESET_SHIFT); in rkclk_set_pll()
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| H A D | clk_rk3128.c | 67 rk_clrreg(&pll->con1, 1 << PLL_PD_SHIFT); in rkclk_set_pll()
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| H A D | clk_rv1108.c | 102 rk_clrreg(&pll->con3, 1 << GLOBAL_POWER_DOWN_SHIFT); in rkclk_set_pll()
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| H A D | clk_rk3399.c | 1027 rk_clrreg(&priv->cru->clksel_con[19], BIT(4)); in rk3399_gmac_set_parent()
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| /openbmc/u-boot/drivers/reset/ |
| H A D | reset-rockchip.c | 72 rk_clrreg(priv->base + (bank * 4), BIT(offset)); in rockchip_reset_deassert()
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| /openbmc/u-boot/drivers/ram/rockchip/ |
| H A D | dmc-rk3368.c | 143 rk_clrreg(&grf->ddrc0_con0, NOC_RSP_ERR_STALL); in ddr_set_noc_spr_err_stall()
151 rk_clrreg(&grf->ddrc0_con0, MSCH0_MAINDDR3_DDR3); in ddr_set_ddr3_mode()
344 rk_clrreg(&cru->softrst_con[10], phy_reset); in ddrctl_reset()
346 rk_clrreg(&cru->softrst_con[10], ctl_reset); in ddrctl_reset()
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| H A D | sdram_rk322x.c | 101 rk_clrreg(&cru->cru_softrst_con[5], 1 << DDRPHY_PSRST_SHIFT | in phy_pctrl_reset()
105 rk_clrreg(&cru->cru_softrst_con[5], 1 << DDRCTRL_PSRST_SHIFT | in phy_pctrl_reset()
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| H A D | sdram_rk3288.c | 453 rk_clrreg(&grf->soc_con0, 1 << (8 + channel)); in set_bandwidth_ratio()
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| /openbmc/u-boot/arch/arm/mach-rockchip/rk3036/ |
| H A D | sdram_rk3036.c | 378 rk_clrreg(&priv->cru->cru_softrst_con[5], 1 << DDRPHY_PSRST_SHIFT | in phy_pctrl_reset()
382 rk_clrreg(&priv->cru->cru_softrst_con[5], 1 << DDRCTRL_PSRST_SHIFT | in phy_pctrl_reset()
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