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Searched refs:riscv (Results 1 – 25 of 228) sorted by relevance

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/openbmc/linux/drivers/gpu/drm/tegra/
H A Driscv.c32 static void riscv_writel(struct tegra_drm_riscv *riscv, u32 value, u32 offset) in riscv_writel() argument
34 writel(value, riscv->regs + offset); in riscv_writel()
37 int tegra_drm_riscv_read_descriptors(struct tegra_drm_riscv *riscv) in tegra_drm_riscv_read_descriptors() argument
39 struct tegra_drm_riscv_descriptor *bl = &riscv->bl_desc; in tegra_drm_riscv_read_descriptors()
40 struct tegra_drm_riscv_descriptor *os = &riscv->os_desc; in tegra_drm_riscv_read_descriptors()
41 const struct device_node *np = riscv->dev->of_node; in tegra_drm_riscv_read_descriptors()
47 dev_err(riscv->dev, "failed to read " name ": %d\n", err); \ in tegra_drm_riscv_read_descriptors()
62 dev_err(riscv->dev, "descriptors not available\n"); in tegra_drm_riscv_read_descriptors()
69 int tegra_drm_riscv_boot_bootrom(struct tegra_drm_riscv *riscv, phys_addr_t image_address, in tegra_drm_riscv_boot_bootrom() argument
76 riscv_writel(riscv, RISCV_BCR_CTRL_CORE_SELECT_RISCV, RISCV_BCR_CTRL); in tegra_drm_riscv_boot_bootrom()
[all …]
/openbmc/linux/arch/riscv/
H A DMakefile58 riscv-march-$(CONFIG_ARCH_RV32I) := rv32ima
59 riscv-march-$(CONFIG_ARCH_RV64I) := rv64ima
60 riscv-march-$(CONFIG_FPU) := $(riscv-march-y)fd
61 riscv-march-$(CONFIG_RISCV_ISA_C) := $(riscv-march-y)c
62 riscv-march-$(CONFIG_RISCV_ISA_V) := $(riscv-march-y)v
68 riscv-march-$(CONFIG_TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI) := $(riscv-march-y)_zicsr_zifencei
72 riscv-march-$(CONFIG_TOOLCHAIN_HAS_ZIHINTPAUSE) := $(riscv-march-y)_zihintpause
76 KBUILD_CFLAGS += -march=$(shell echo $(riscv-march-y) | sed -E 's/(rv32ima|rv64ima)fd([^v_]*)v?/\1\…
78 KBUILD_AFLAGS += -march=$(riscv-march-y)
95 KBUILD_CFLAGS += $(call cc-option,-mno-riscv-attribute)
[all …]
/openbmc/qemu/configs/targets/
H A Driscv32-linux-user.mak2 TARGET_BASE_ARCH=riscv
3 TARGET_ABI_DIR=riscv
4 TARGET_XML_FILES= gdb-xml/riscv-32bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml gdb-xml/riscv-64bit-fpu.x…
8 TARGET_SYSTBL_ABI=common,32,riscv,memfd_secret
H A Driscv64-linux-user.mak2 TARGET_BASE_ARCH=riscv
3 TARGET_ABI_DIR=riscv
4 TARGET_XML_FILES= gdb-xml/riscv-64bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml gdb-xml/riscv-64bit-fpu.x…
8 TARGET_SYSTBL_ABI=common,64,riscv,rlimit,memfd_secret
H A Driscv64-softmmu.mak2 TARGET_BASE_ARCH=riscv
5 …l/riscv-64bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-64bit-…
H A Driscv64-bsd-user.mak2 TARGET_BASE_ARCH=riscv
3 TARGET_ABI_DIR=riscv
4 TARGET_XML_FILES= gdb-xml/riscv-64bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml gdb-xml/riscv-64bit-fpu.x…
H A Driscv32-softmmu.mak2 TARGET_BASE_ARCH=riscv
4 TARGET_XML_FILES= gdb-xml/riscv-32bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml gdb-xml/riscv-64bit-fpu.x…
/openbmc/linux/arch/riscv/boot/dts/sifive/
H A Dfu540-c000.dtsi26 compatible = "sifive,e51", "sifive,rocket0", "riscv";
32 riscv,isa = "rv64imac";
36 compatible = "riscv,cpu-intc";
41 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
53 mmu-type = "riscv,sv39";
55 riscv,isa = "rv64imafdc";
60 compatible = "riscv,cpu-intc";
65 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
77 mmu-type = "riscv,sv39";
79 riscv,isa = "rv64imafdc";
[all …]
H A Dfu740-c000.dtsi26 compatible = "sifive,bullet0", "riscv";
33 riscv,isa = "rv64imac";
37 compatible = "riscv,cpu-intc";
42 compatible = "sifive,bullet0", "riscv";
54 mmu-type = "riscv,sv39";
57 riscv,isa = "rv64imafdc";
61 compatible = "riscv,cpu-intc";
66 compatible = "sifive,bullet0", "riscv";
78 mmu-type = "riscv,sv39";
81 riscv,isa = "rv64imafdc";
[all …]
/openbmc/openbmc/poky/meta/recipes-devtools/qemu/qemu/
H A Dfix-strerrorname_np.patch4 Subject: [PATCH] target/riscv/kvm: do not use non-portable strerrorname_np()
13 Fixes: commit 082e9e4a58ba (target/riscv/kvm: improve 'init_multiext_cfg' error
19 target/riscv/kvm/kvm-cpu.c | 3 +--
22 diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
24 --- a/target/riscv/kvm/kvm-cpu.c
25 +++ b/target/riscv/kvm/kvm-cpu.c
/openbmc/u-boot/arch/riscv/dts/
H A Dae350_32.dts27 compatible = "riscv";
28 riscv,isa = "rv32imafdc";
29 mmu-type = "riscv,sv32";
36 compatible = "riscv,cpu-intc";
49 compatible = "andestech,riscv-ae350-soc";
53 compatible = "riscv,plic0";
58 riscv,ndev=<71>;
63 compatible = "riscv,plic1";
68 riscv,ndev=<1>;
73 compatible = "riscv,plmt0";
H A Dae350_64.dts27 compatible = "riscv";
28 riscv,isa = "rv64imafdc";
29 mmu-type = "riscv,sv39";
36 compatible = "riscv,cpu-intc";
49 compatible = "andestech,riscv-ae350-soc";
53 compatible = "riscv,plic0";
58 riscv,ndev=<71>;
63 compatible = "riscv,plic1";
68 riscv,ndev=<1>;
73 compatible = "riscv,plmt0";
/openbmc/linux/arch/riscv/boot/dts/thead/
H A Dth1520.dtsi20 compatible = "thead,c910", "riscv";
22 riscv,isa = "rv64imafdc";
31 mmu-type = "riscv,sv39";
34 compatible = "riscv,cpu-intc";
41 compatible = "thead,c910", "riscv";
43 riscv,isa = "rv64imafdc";
52 mmu-type = "riscv,sv39";
55 compatible = "riscv,cpu-intc";
62 compatible = "thead,c910", "riscv";
64 riscv,isa = "rv64imafdc";
[all …]
/openbmc/openbmc/poky/meta/recipes-multimedia/ffmpeg/ffmpeg/
H A D0001-lavc-h264dsp-move-RISC-V-fn-pointers-to-.data.rel.ro.patch11 libavcodec/riscv/h264dsp_rvv.S | 2 +-
14 diff --git a/libavcodec/riscv/h264dsp_rvv.S b/libavcodec/riscv/h264dsp_rvv.S
16 --- a/libavcodec/riscv/h264dsp_rvv.S
17 +++ b/libavcodec/riscv/h264dsp_rvv.S
/openbmc/qemu/docs/specs/
H A Driscv-iommu.rst9 The emulation includes a PCI reference device, riscv-iommu-pci, that QEMU
13 riscv-iommu-pci reference device
27 $ qemu-system-riscv64 -M virt -device riscv-iommu-pci,[optional_pci_opts] (...)
52 -device riscv-iommu-pci,addr=1.0,vendor-id=0x1efd,device-id=0xedf1 \
61 -device riscv-iommu-pci,addr=1.0,vendor-id=0x1efd,device-id=0xedf1 \
68 use the riscv-iommu-pci device with the existing kernel support we need to emulate
74 -device riscv-iommu-pci,vendor-id=0x1efd,device-id=0xedf1 (...)
86 .. _iommu1.0: https://github.com/riscv-non-isa/riscv-iommu/releases/download/v1.0/riscv-iommu.pdf
88 .. _linux-v8: https://lore.kernel.org/linux-riscv/cover.1718388908.git.tjeznach@rivosinc.com/
/openbmc/linux/arch/riscv/boot/dts/microchip/
H A Dmpfs.dtsi18 compatible = "sifive,e51", "sifive,rocket0", "riscv";
24 riscv,isa = "rv64imac";
30 compatible = "riscv,cpu-intc";
36 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
48 mmu-type = "riscv,sv39";
50 riscv,isa = "rv64imafdc";
58 compatible = "riscv,cpu-intc";
64 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
76 mmu-type = "riscv,sv39";
78 riscv,isa = "rv64imafdc";
[all …]
/openbmc/linux/Documentation/riscv/
H A Dacpi.rst9 "riscv-isa-release-1239329-2023-05-23" (commit 1239329
10 ) <https://github.com/riscv/riscv-isa-manual/releases/tag/riscv-isa-release-1239329-2023-05-23>`_
/openbmc/linux/arch/riscv/boot/dts/renesas/
H A Dr9a07g043f.dtsi21 compatible = "andestech,ax45mp", "riscv";
26 riscv,isa = "rv64imafdc";
27 mmu-type = "riscv,sv39";
37 compatible = "riscv,cpu-intc";
51 riscv,ndev = <511>;
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-devtools/concurrencykit/concurrencykit/
H A D0001-build-Use-ilp32d-abi-on-riscv32-and-lp64d-on-rv64.patch12 build/ck.build.riscv | 2 +-
16 diff --git a/build/ck.build.riscv b/build/ck.build.riscv
18 --- a/build/ck.build.riscv
19 +++ b/build/ck.build.riscv
/openbmc/u-boot/arch/riscv/
H A DMakefile33 head-y := arch/riscv/cpu/start.o
35 libs-y += arch/riscv/cpu/
36 libs-y += arch/riscv/cpu/$(CPU)/
37 libs-y += arch/riscv/lib/
/openbmc/linux/arch/riscv/boot/dts/allwinner/
H A Dsun20i-d1s.dtsi15 compatible = "thead,c906", "riscv";
25 mmu-type = "riscv,sv39";
27 riscv,isa = "rv64imafdc";
31 compatible = "riscv,cpu-intc";
70 riscv,ndev = <175>;
/openbmc/openbmc/meta-arm/meta-arm/recipes-security/optee/optee-os/
H A D0002-link.mk-use-CFLAGS-with-version.o.patch12 core/arch/riscv/kernel/link.mk | 2 +-
30 diff --git a/core/arch/riscv/kernel/link.mk b/core/arch/riscv/kernel/link.mk
32 --- a/core/arch/riscv/kernel/link.mk
33 +++ b/core/arch/riscv/kernel/link.mk
H A D0003-link.mk-generate-version.o-in-link-out-dir.patch19 core/arch/riscv/kernel/link.mk | 5 +++--
46 diff --git a/core/arch/riscv/kernel/link.mk b/core/arch/riscv/kernel/link.mk
48 --- a/core/arch/riscv/kernel/link.mk
49 +++ b/core/arch/riscv/kernel/link.mk
/openbmc/linux/arch/riscv/boot/dts/starfive/
H A Djh7100.dtsi21 compatible = "sifive,u74-mc", "riscv";
34 mmu-type = "riscv,sv39";
35 riscv,isa = "rv64imafdc";
39 compatible = "riscv,cpu-intc";
46 compatible = "sifive,u74-mc", "riscv";
59 mmu-type = "riscv,sv39";
60 riscv,isa = "rv64imafdc";
64 compatible = "riscv,cpu-intc";
158 riscv,ndev = <133>;
/openbmc/linux/arch/riscv/purgatory/
H A DMakefile16 $(obj)/memcpy.o: $(srctree)/arch/riscv/lib/memcpy.S FORCE
19 $(obj)/memset.o: $(srctree)/arch/riscv/lib/memset.S FORCE
22 $(obj)/strcmp.o: $(srctree)/arch/riscv/lib/strcmp.S FORCE
25 $(obj)/strlen.o: $(srctree)/arch/riscv/lib/strlen.S FORCE
28 $(obj)/strncmp.o: $(srctree)/arch/riscv/lib/strncmp.S FORCE

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