Home
last modified time | relevance | path

Searched refs:reset_addr (Results 1 – 15 of 15) sorted by relevance

/openbmc/linux/lib/
H A Dstmp_device.c38 int stmp_reset_block(void __iomem *reset_addr) in stmp_reset_block() argument
44 ret = stmp_clear_poll_bit(reset_addr, STMP_MODULE_SFTRST); in stmp_reset_block()
49 writel(STMP_MODULE_CLKGATE, reset_addr + STMP_OFFSET_REG_CLR); in stmp_reset_block()
52 writel(STMP_MODULE_SFTRST, reset_addr + STMP_OFFSET_REG_SET); in stmp_reset_block()
56 while ((!(readl(reset_addr) & STMP_MODULE_CLKGATE)) && --timeout) in stmp_reset_block()
62 ret = stmp_clear_poll_bit(reset_addr, STMP_MODULE_SFTRST); in stmp_reset_block()
67 ret = stmp_clear_poll_bit(reset_addr, STMP_MODULE_CLKGATE); in stmp_reset_block()
74 pr_err("%s(%p): module reset timeout\n", __func__, reset_addr); in stmp_reset_block()
/openbmc/linux/arch/arm/mach-mxs/
H A Dmach-mxs.c59 static void __iomem *reset_addr; variable
360 reset_addr = of_iomap(np, 0); in mxs_restart_init()
361 if (!reset_addr) in mxs_restart_init()
365 reset_addr += MX23_CLKCTRL_RESET_OFFSET; in mxs_restart_init()
367 reset_addr += MX28_CLKCTRL_RESET_OFFSET; in mxs_restart_init()
453 if (reset_addr) { in mxs_restart()
455 __mxs_setl(MXS_CLKCTRL_RESET_CHIP, reset_addr); in mxs_restart()
/openbmc/linux/drivers/net/can/sja1000/
H A Dplx_pci.c494 void __iomem *reset_addr; in plx_pci_reset_marathon_pci() local
501 reset_addr = pci_iomap(pdev, reset_bar[i], 0); in plx_pci_reset_marathon_pci()
502 if (!reset_addr) { in plx_pci_reset_marathon_pci()
507 iowrite8(0x1, reset_addr); in plx_pci_reset_marathon_pci()
509 pci_iounmap(pdev, reset_addr); in plx_pci_reset_marathon_pci()
518 void __iomem *reset_addr; in plx_pci_reset_marathon_pcie() local
533 reset_addr = addr + chan_map->offset + in plx_pci_reset_marathon_pcie()
535 iowrite8(0x1, reset_addr); in plx_pci_reset_marathon_pcie()
/openbmc/u-boot/arch/nios2/cpu/
H A Dcpu.c35 nios2_callr(gd->arch.reset_addr); in do_reset()
117 gd->arch.reset_addr = fdtdec_get_int(blob, node, in altera_nios2_probe()
/openbmc/linux/arch/m68k/atari/
H A Dconfig.c495 long reset_addr; in atari_reset() local
501 reset_addr = MACH_IS_MEDUSA || MACH_IS_AB40 ? 0xe00030 : in atari_reset()
564 : "a" (reset_addr) in atari_reset()
571 : "m" (tc_val), "a" (reset_addr)); in atari_reset()
/openbmc/u-boot/arch/nios2/include/asm/
H A Dglobal_data.h15 u32 reset_addr; member
/openbmc/linux/arch/nios2/include/asm/
H A Dcpuinfo.h37 u32 reset_addr; member
/openbmc/linux/arch/nios2/kernel/
H A Dprocess.c45 pr_notice("Machine restart (%08x)...\n", cpuinfo.reset_addr); in machine_restart()
50 : "r" (cpuinfo.reset_addr) in machine_restart()
H A Dcpuinfo.c107 cpuinfo.reset_addr = fcpu(cpu, "altr,reset-addr"); in setup_cpuinfo()
/openbmc/linux/include/linux/
H A Drmi.h286 int (*reset)(struct rmi_transport_dev *xport, u16 reset_addr);
/openbmc/linux/drivers/mtd/nand/raw/gpmi-nand/
H A Dgpmi-nand.c77 static int gpmi_reset_block(void __iomem *reset_addr, bool just_enable) in gpmi_reset_block() argument
83 ret = clear_poll_bit(reset_addr, MODULE_SFTRST); in gpmi_reset_block()
88 writel(MODULE_CLKGATE, reset_addr + MXS_CLR_ADDR); in gpmi_reset_block()
92 writel(MODULE_SFTRST, reset_addr + MXS_SET_ADDR); in gpmi_reset_block()
96 while ((!(readl(reset_addr) & MODULE_CLKGATE)) && --timeout) in gpmi_reset_block()
103 ret = clear_poll_bit(reset_addr, MODULE_SFTRST); in gpmi_reset_block()
108 ret = clear_poll_bit(reset_addr, MODULE_CLKGATE); in gpmi_reset_block()
115 pr_err("%s(%p): module reset timeout\n", __func__, reset_addr); in gpmi_reset_block()
/openbmc/linux/drivers/input/rmi4/
H A Drmi_smbus.c265 static int rmi_smb_reset(struct rmi_transport_dev *xport, u16 reset_addr) in rmi_smb_reset() argument
/openbmc/qemu/target/i386/
H A Dsev.c80 uint32_t reset_addr; member
1734 if (!info->reset_addr) { in sev_es_parse_reset_block()
1739 *addr = info->reset_addr; in sev_es_parse_reset_block()
/openbmc/linux/drivers/hid/
H A Dhid-rmi.c488 static int rmi_hid_reset(struct rmi_transport_dev *xport, u16 reset_addr) in rmi_hid_reset() argument
/openbmc/qemu/hw/misc/
H A Dtrace-events4 allwinner_cpucfg_cpu_reset(uint8_t cpu_id, uint32_t reset_addr) "id %u, reset_addr 0x%" PRIx32