| /openbmc/linux/drivers/bus/fsl-mc/ |
| H A D | fsl-mc-allocator.c | 37 struct fsl_mc_resource_pool *res_pool; in fsl_mc_resource_pool_add_device() local
49 res_pool = &mc_bus->resource_pools[pool_type]; in fsl_mc_resource_pool_add_device()
50 if (res_pool->type != pool_type) in fsl_mc_resource_pool_add_device()
52 if (res_pool->mc_bus != mc_bus) in fsl_mc_resource_pool_add_device()
55 mutex_lock(&res_pool->mutex); in fsl_mc_resource_pool_add_device()
57 if (res_pool->max_count < 0) in fsl_mc_resource_pool_add_device()
59 if (res_pool->free_count < 0 || in fsl_mc_resource_pool_add_device()
60 res_pool->free_count > res_pool->max_count) in fsl_mc_resource_pool_add_device()
75 resource->parent_pool = res_pool; in fsl_mc_resource_pool_add_device()
77 list_add_tail(&resource->node, &res_pool->free_list); in fsl_mc_resource_pool_add_device()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn31/ |
| H A D | dcn31_hwseq.c | 92 dc->res_pool->mpc->funcs->set_mpc_mem_lp_mode) in enable_memory_low_power()
93 dc->res_pool->mpc->funcs->set_mpc_mem_lp_mode(dc->res_pool->mpc); in enable_memory_low_power()
96 …if (dc->debug.enable_mem_low_power.bits.vpg && dc->res_pool->stream_enc[0]->vpg->funcs->vpg_powerd… in enable_memory_low_power()
98 for (i = 0; i < dc->res_pool->stream_enc_count; i++) in enable_memory_low_power()
99 dc->res_pool->stream_enc[i]->vpg->funcs->vpg_powerdown(dc->res_pool->stream_enc[i]->vpg); in enable_memory_low_power()
101 for (i = 0; i < dc->res_pool->hpo_dp_stream_enc_count; i++) in enable_memory_low_power()
102 …dc->res_pool->hpo_dp_stream_enc[i]->vpg->funcs->vpg_powerdown(dc->res_pool->hpo_dp_stream_enc[i]->… in enable_memory_low_power()
110 struct abm **abms = dc->res_pool->multiple_abms; in dcn31_init_hw()
113 struct resource_pool *res_pool = dc->res_pool; in dcn31_init_hw() local
126 if (res_pool->dccg->funcs->dccg_init) in dcn31_init_hw()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn201/ |
| H A D | dcn201_hwseq.c | 183 ASSERT(opp_id_src0 < dc->res_pool->res_cap->num_opp); in dcn201_init_blank()
184 opp = dc->res_pool->opps[opp_id_src0]; in dcn201_init_blank()
225 struct resource_pool *res_pool = dc->res_pool; in dcn201_init_hw() local
228 if (res_pool->dccg->funcs->dccg_init) in dcn201_init_hw()
229 res_pool->dccg->funcs->dccg_init(res_pool->dccg); in dcn201_init_hw()
237 res_pool->ref_clocks.xtalin_clock_inKhz = in dcn201_init_hw()
240 if (res_pool->dccg && res_pool->hubbub) { in dcn201_init_hw()
241 (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg, in dcn201_init_hw()
243 &res_pool->ref_clocks.dccg_ref_clock_inKhz); in dcn201_init_hw()
245 (res_pool->hubbub->funcs->get_dchub_ref_freq)(res_pool->hubbub, in dcn201_init_hw()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn30/ |
| H A D | dcn30_hwseq.c | 98 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; in dcn30_set_mpc_shaper_3dlut()
194 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; in dcn30_set_output_transfer_func()
236 ASSERT(wb_info->mpcc_inst < dc->res_pool->mpcc_count); in dcn30_set_writeback()
237 mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst]; in dcn30_set_writeback()
241 dc->res_pool->mpc->funcs->set_dwb_mux(dc->res_pool->mpc, in dcn30_set_writeback()
254 dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst]; in dcn30_update_writeback()
276 dwb = dc->res_pool->dwbc[wb_info[i].dwb_pipe_inst]; in dcn30_mmhubbub_warmup()
290 mcif_wb = dc->res_pool->mcif_wb[0]; in dcn30_mmhubbub_warmup()
305 dwb = dc->res_pool->dwbc[wb_info[i].dwb_pipe_inst]; in dcn30_mmhubbub_warmup()
306 mcif_wb = dc->res_pool->mcif_wb[wb_info[i].dwb_pipe_inst]; in dcn30_mmhubbub_warmup()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn32/ |
| H A D | dcn32_hwseq.c | 228 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_calculate_cab_allocation()
347 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_commit_subvp_config()
378 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_subvp_pipe_control_lock()
398 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_subvp_pipe_control_lock()
444 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; in dcn32_set_mpc_shaper_3dlut()
480 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; in dcn32_set_mcm_luts()
525 struct mpc *mpc = dc->res_pool->mpc; in dcn32_set_input_transfer_func()
567 struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc; in dcn32_set_output_transfer_func()
608 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_update_force_pstate()
629 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_update_force_pstate()
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| H A D | dcn32_resource_helpers.c | 128 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_merge_pipes_for_subvp()
147 dcn20_release_dsc(&context->res_ctx, dc->res_pool, &pipe->stream_res.dsc); in dcn32_merge_pipes_for_subvp()
173 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_all_pipes_have_stream_and_plane()
190 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_subvp_in_use()
215 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_any_surfaces_rotated()
309 for (j = 0; j < dc->res_pool->pipe_count; j++) { in dcn32_determine_det_override()
320 for (k = 0; k < dc->res_pool->pipe_count; k++) { in dcn32_determine_det_override()
329 for (k = 0; k < dc->res_pool->pipe_count; k++) { in dcn32_determine_det_override()
339 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_determine_det_override()
346 for (i = 0; i < dc->res_pool->pipe_count; i++) in dcn32_determine_det_override()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn20/ |
| H A D | dcn20_hwseq.c | 72 if (dc->res_pool->gsl_groups.gsl_0 == 0) in find_free_gsl_group()
74 if (dc->res_pool->gsl_groups.gsl_1 == 0) in find_free_gsl_group()
76 if (dc->res_pool->gsl_groups.gsl_2 == 0) in find_free_gsl_group()
122 dc->res_pool->gsl_groups.gsl_0 = 1; in dcn20_setup_gsl_group_as_lock()
126 dc->res_pool->gsl_groups.gsl_1 = 1; in dcn20_setup_gsl_group_as_lock()
130 dc->res_pool->gsl_groups.gsl_2 = 1; in dcn20_setup_gsl_group_as_lock()
148 dc->res_pool->gsl_groups.gsl_0 = 0; in dcn20_setup_gsl_group_as_lock()
152 dc->res_pool->gsl_groups.gsl_1 = 0; in dcn20_setup_gsl_group_as_lock()
156 dc->res_pool->gsl_groups.gsl_2 = 0; in dcn20_setup_gsl_group_as_lock()
310 if (opp_id_src0 >= dc->res_pool->res_cap->num_opp) { in dcn20_init_blank()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn10/ |
| H A D | dcn10_hw_sequencer.c | 84 const uint32_t ref_clk_mhz = dc_ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000; in print_microsec()
102 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn10_lock_all_pipes()
147 dc->res_pool->hubbub->funcs->wm_read_state(dc->res_pool->hubbub, &wm); in dcn10_log_hubbub_state()
171 struct resource_pool *pool = dc->res_pool; in dcn10_log_hubp_states()
286 struct resource_pool *pool = dc->res_pool; in dcn10_log_hw_state()
759 struct hubp *hubp = dc->res_pool->hubps[0]; in undo_DEGVIDCN10_253_wa()
779 struct hubp *hubp = dc->res_pool->hubps[0]; in apply_DEGVIDCN10_253_wa()
788 for (i = 0; i < dc->res_pool->pipe_count; i++) { in apply_DEGVIDCN10_253_wa()
789 if (!dc->res_pool->hubps[i]->power_gated) in apply_DEGVIDCN10_253_wa()
816 if (dc->res_pool->hubbub->funcs->is_allow_self_refresh_enabled) in dcn10_bios_golden_init()
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| H A D | dcn10_hw_sequencer_debug.c | 81 const uint32_t ref_clk_mhz = dc_ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000; in dcn10_get_hubbub_state()
85 dc->res_pool->hubbub->funcs->wm_read_state(dc->res_pool->hubbub, &wm); in dcn10_get_hubbub_state()
113 struct resource_pool *pool = dc->res_pool; in dcn10_get_hubp_states()
119 const uint32_t ref_clk_mhz = dc_ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000; in dcn10_get_hubp_states()
191 struct resource_pool *pool = dc->res_pool; in dcn10_get_rq_states()
233 struct resource_pool *pool = dc->res_pool; in dcn10_get_dlg_states()
290 struct resource_pool *pool = dc->res_pool; in dcn10_get_ttu_states()
330 struct resource_pool *pool = dc->res_pool; in dcn10_get_cm_states()
385 struct resource_pool *pool = dc->res_pool; in dcn10_get_mpcc_states()
416 struct resource_pool *pool = dc->res_pool; in dcn10_get_otg_states()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn314/ |
| H A D | dcn314_hwseq.c | 188 struct mpc *mpc = dc->res_pool->mpc; in dcn314_update_odm()
250 hws->ctx->dc->res_pool->dccg->funcs->enable_dsc && in dcn314_dsc_pg_control()
252 hws->ctx->dc->res_pool->dccg->funcs->enable_dsc( in dcn314_dsc_pg_control()
253 hws->ctx->dc->res_pool->dccg, dsc_inst); in dcn314_dsc_pg_control()
301 if (hws->ctx->dc->res_pool->dccg->funcs->disable_dsc && !power_on) in dcn314_dsc_pg_control()
302 hws->ctx->dc->res_pool->dccg->funcs->disable_dsc( in dcn314_dsc_pg_control()
303 hws->ctx->dc->res_pool->dccg, dsc_inst); in dcn314_dsc_pg_control()
399 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn314_resync_fifo_dccg_dio()
412 hws->ctx->dc->res_pool->dccg->funcs->trigger_dio_fifo_resync(hws->ctx->dc->res_pool->dccg); in dcn314_resync_fifo_dccg_dio()
414 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn314_resync_fifo_dccg_dio()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/core/ |
| H A D | dc.c | 232 for (i = 0; i < dc->res_pool->usb4_dpia_count; i++) { in create_links()
304 unsigned int num_usb4_dpia = dc->res_pool->res_cap->num_usb4_dpia; in create_link_encoders()
305 unsigned int num_dig_link_enc = dc->res_pool->res_cap->num_dig_link_enc; in create_link_encoders()
318 if (num_dig_link_enc > dc->res_pool->dig_link_enc_count) { in create_link_encoders()
320 struct link_encoder *link_enc = dc->res_pool->link_encoders[i]; in create_link_encoders()
322 if (!link_enc && dc->res_pool->funcs->link_enc_create_minimal) { in create_link_encoders()
323 link_enc = dc->res_pool->funcs->link_enc_create_minimal(dc->ctx, in create_link_encoders()
326 dc->res_pool->link_encoders[i] = link_enc; in create_link_encoders()
327 dc->res_pool->dig_link_enc_count++; in create_link_encoders()
348 if (!dc->res_pool) in destroy_link_encoders()
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| H A D | dc_resource.c | 200 struct resource_pool *res_pool = NULL; in dc_create_resource_pool() local
205 res_pool = dce60_create_resource_pool( in dc_create_resource_pool()
209 res_pool = dce61_create_resource_pool( in dc_create_resource_pool()
213 res_pool = dce64_create_resource_pool( in dc_create_resource_pool()
218 res_pool = dce80_create_resource_pool( in dc_create_resource_pool()
222 res_pool = dce81_create_resource_pool( in dc_create_resource_pool()
226 res_pool = dce83_create_resource_pool( in dc_create_resource_pool()
230 res_pool = dce100_create_resource_pool( in dc_create_resource_pool()
234 res_pool = dce110_create_resource_pool( in dc_create_resource_pool()
240 res_pool = dce112_create_resource_pool( in dc_create_resource_pool()
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| H A D | dc_link_enc_cfg.c | 40 for (i = 0; i < stream->ctx->dc->res_pool->res_cap->num_dig_link_enc; i++) { in is_dig_link_enc_stream()
41 link_enc = stream->ctx->dc->res_pool->link_encoders[i]; in is_dig_link_enc_stream()
159 stream->link_enc = stream->ctx->dc->res_pool->link_encoders[eng_idx]; in add_link_enc_assignment()
180 for (i = 0; i < ctx->dc->res_pool->res_cap->num_dig_link_enc; i++) { in find_first_avail_link_enc()
189 for (i = 0; i < ctx->dc->res_pool->res_cap->num_dig_link_enc; i++) { in find_first_avail_link_enc()
253 link_enc = link->dc->res_pool->link_encoders[assignment.eng_id - ENGINE_ID_DIGA]; in get_link_enc_used_by_link()
272 for (i = 0; i < dc->res_pool->res_cap->num_dig_link_enc; i++) { in clear_enc_assignments()
273 if (dc->res_pool->link_encoders[i]) in clear_enc_assignments()
311 dc->res_pool->funcs->link_enc_unassign(state, dc->current_state->streams[i]); in link_enc_cfg_link_encs_assign()
522 link_enc = link->dc->res_pool->link_encoders[assignment.eng_id - ENGINE_ID_DIGA]; in link_enc_cfg_get_link_enc_used_by_link()
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| H A D | dc_link_exports.c | 146 if (dc->res_pool->oem_device) in dc_is_oem_i2c_device_present()
148 dc->res_pool, in dc_is_oem_i2c_device_present()
149 dc->res_pool->oem_device, in dc_is_oem_i2c_device_present()
165 dc->res_pool, in dc_submit_i2c()
174 struct ddc_service *ddc = dc->res_pool->oem_device; in dc_submit_i2c_oem()
178 dc->res_pool, in dc_submit_i2c_oem()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/link/hwss/ |
| H A D | link_hwss_hpo_dp.c | 118 if (link->dc->res_pool->dccg->funcs->set_symclk32_le_root_clock_gating) in enable_hpo_dp_link_output()
119 link->dc->res_pool->dccg->funcs->set_symclk32_le_root_clock_gating( in enable_hpo_dp_link_output()
120 link->dc->res_pool->dccg, in enable_hpo_dp_link_output()
142 if (link->dc->res_pool->dccg->funcs->set_symclk32_le_root_clock_gating) in disable_hpo_dp_link_output()
143 link->dc->res_pool->dccg->funcs->set_symclk32_le_root_clock_gating( in disable_hpo_dp_link_output()
144 link->dc->res_pool->dccg, in disable_hpo_dp_link_output()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/ |
| H A D | dc_edid_parser.c | 35 struct dmcu *dmcu = dc->res_pool->dmcu; in dc_edid_parser_send_cea()
52 struct dmcu *dmcu = dc->res_pool->dmcu; in dc_edid_parser_recv_cea_ack()
68 struct dmcu *dmcu = dc->res_pool->dmcu; in dc_edid_parser_recv_amd_vsdb()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dce110/ |
| H A D | dce110_hw_sequencer.c | 210 unsigned int underlay_idx = dc->res_pool->underlay_pipe_index; in dce110_enable_display_power_gating()
1152 struct dccg *dccg = dc->res_pool->dccg; in dce110_disable_stream()
1632 for (i = 0; i < dc->res_pool->timing_generator_count; i++) { in power_down_controllers()
1633 dc->res_pool->timing_generators[i]->funcs->disable_crtc( in power_down_controllers()
1634 dc->res_pool->timing_generators[i]); in power_down_controllers()
1642 if (dc->res_pool->dp_clock_source->funcs->cs_power_down( in power_down_clock_sources()
1643 dc->res_pool->dp_clock_source) == false) in power_down_clock_sources()
1646 for (i = 0; i < dc->res_pool->clk_src_count; i++) { in power_down_clock_sources()
1647 if (dc->res_pool->clock_sources[i]->funcs->cs_power_down( in power_down_clock_sources()
1648 dc->res_pool->clock_sources[i]) == false) in power_down_clock_sources()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/link/protocols/ |
| H A D | link_edp_panel_control.c | 547 struct dmcu *dmcu = dc->res_pool->dmcu; in edp_set_psr_allow_active()
548 struct dmub_psr *psr = dc->res_pool->psr; in edp_set_psr_allow_active()
595 struct dmcu *dmcu = dc->res_pool->dmcu; in edp_get_psr_state()
596 struct dmub_psr *psr = dc->res_pool->psr; in edp_get_psr_state()
666 dmcu = dc->res_pool->dmcu; in edp_setup_psr()
667 psr = dc->res_pool->psr; in edp_setup_psr()
770 link->dc->res_pool->timing_generator_count; in edp_setup_psr()
845 struct dmub_psr *psr = dc->res_pool->psr; in edp_get_psr_residency()
860 struct dmub_psr *psr = dc->res_pool->psr; in edp_set_sink_vtotal_in_psr_active()
874 struct dmub_replay *replay = dc->res_pool->replay; in edp_set_replay_allow_active()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn21/ |
| H A D | dcn21_hwseq.c | 83 return dc->res_pool->hubbub->funcs->init_dchub_sys_ctx(dc->res_pool->hubbub, &config); in dcn21_init_sys_ctx()
184 struct dmcu *dmcu = pipe_ctx->stream->ctx->dc->res_pool->dmcu; in dcn21_set_abm_immediate_disable()
211 struct dmcu *dmcu = pipe_ctx->stream->ctx->dc->res_pool->dmcu; in dcn21_set_pipe()
253 if (dc->dc->res_pool->dmcu) { in dcn21_set_backlight_level()
286 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn21_is_abm_supported()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/link/ |
| H A D | link_factory.c | 412 link->dc->res_pool->link_encoders[link->eng_id - ENGINE_ID_DIGA] = NULL; in link_destruct()
413 link->dc->res_pool->dig_link_enc_count--; in link_destruct()
517 if (link->dc->res_pool->funcs->link_init) in construct_phy()
518 link->dc->res_pool->funcs->link_init(link); in construct_phy()
630 link->dc->res_pool->funcs->link_enc_create(dc_ctx, &enc_init_data); in construct_phy()
644 link->dc->res_pool->link_encoders[link->eng_id - ENGINE_ID_DIGA] = link->link_enc; in construct_phy()
645 link->dc->res_pool->dig_link_enc_count++; in construct_phy()
649 if (link->dc->res_pool->funcs->panel_cntl_create && in construct_phy()
656 link->dc->res_pool->funcs->panel_cntl_create( in construct_phy()
816 if (link->dc->res_pool->funcs->get_preferred_eng_id_dpia) in construct_dpia()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/ |
| H A D | dcn20_clk_mgr.c | 110 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) { in dcn20_update_clocks_update_dpp_dto()
152 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) { in dcn20_update_clocks_update_dentist()
155 struct dccg *dccg = clk_mgr->base.ctx->dc->res_pool->dccg; in dcn20_update_clocks_update_dentist()
183 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) { in dcn20_update_clocks_update_dentist()
185 struct dccg *dccg = clk_mgr->base.ctx->dc->res_pool->dccg; in dcn20_update_clocks_update_dentist()
229 struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu; in dcn2_update_clocks()
247 if (dc->res_pool->pp_smu) in dcn2_update_clocks()
248 pp_smu = &dc->res_pool->pp_smu->nv_funcs; in dcn2_update_clocks()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| H A D | dcn31_fpu.c | 514 dc->res_pool->funcs->update_soc_for_wm_a(dc, context); in dcn31_calculate_wm_and_dlg_fp()
529 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { in dcn31_calculate_wm_and_dlg_fp()
564 for (i = 0; i < dc->res_pool->pipe_count; i++) in dcn31_calculate_wm_and_dlg_fp()
568 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { in dcn31_calculate_wm_and_dlg_fp()
595 dcn3_1_ip.max_num_otg = dc->res_pool->res_cap->num_timing_generator; in dcn31_update_bw_bounding_box()
596 dcn3_1_ip.max_num_dpp = dc->res_pool->pipe_count; in dcn31_update_bw_bounding_box()
667 dcn3_15_ip.max_num_otg = dc->res_pool->res_cap->num_timing_generator; in dcn315_update_bw_bounding_box()
668 dcn3_15_ip.max_num_dpp = dc->res_pool->pipe_count; in dcn315_update_bw_bounding_box()
734 dcn3_16_ip.max_num_otg = dc->res_pool->res_cap->num_timing_generator; in dcn316_update_bw_bounding_box()
735 dcn3_16_ip.max_num_dpp = dc->res_pool->pipe_count; in dcn316_update_bw_bounding_box()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dce100/ |
| H A D | dce100_hw_sequencer.c | 112 dce110_set_safe_displaymarks(&context->res_ctx, dc->res_pool); in dce100_prepare_bandwidth()
124 dce110_set_safe_displaymarks(&context->res_ctx, dc->res_pool); in dce100_optimize_bandwidth()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| H A D | dcn32_fpu.c | 329 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_helper_populate_phantom_dlg_params()
558 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_set_phantom_stream_timing()
635 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_get_num_free_pipes()
646 free_pipes = dc->res_pool->pipe_count - num_pipes; in dcn32_get_num_free_pipes()
680 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_assign_subvp_pipe()
752 unsigned int min_pipe_split = dc->res_pool->pipe_count + 1; // init as max number of pipes + 1 in dcn32_enough_pipes_for_subvp()
755 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_enough_pipes_for_subvp()
776 if (free_pipes >= min_pipe_split && free_pipes < dc->res_pool->pipe_count) in dcn32_enough_pipes_for_subvp()
805 for (i = 0; i < dc->res_pool->pipe_count; i++) { in subvp_subvp_schedulable()
884 for (i = 0; i < dc->res_pool->pipe_count; i++) { in subvp_drr_schedulable()
[all …]
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dml/dcn314/ |
| H A D | dcn314_fpu.c | 195 dcn3_14_ip.max_num_otg = dc->res_pool->res_cap->num_timing_generator; in dcn314_update_bw_bounding_box_fpu()
196 dcn3_14_ip.max_num_dpp = dc->res_pool->pipe_count; in dcn314_update_bw_bounding_box_fpu()
321 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) { in dcn314_populate_dml_pipes_from_context_fpu()
357 … pipes[i].pipe.src.hostvm = dc->vm_pa_config.is_hvm_enabled || dc->res_pool->hubbub->riommu_active; in dcn314_populate_dml_pipes_from_context_fpu()
412 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn314_populate_dml_pipes_from_context_fpu()
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