/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn302/ |
H A D | dcn302_resource.c | 708 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn302_dwbc_create() 743 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn302_mmhubbub_create() 1004 for (i = 0; i < pool->res_cap->num_dsc; i++) { in dcn302_resource_destruct() 1034 for (i = 0; i < pool->res_cap->num_ddc; i++) { in dcn302_resource_destruct() 1047 for (i = 0; i < pool->res_cap->num_opp; i++) { in dcn302_resource_destruct() 1052 for (i = 0; i < pool->res_cap->num_timing_generator; i++) { in dcn302_resource_destruct() 1059 for (i = 0; i < pool->res_cap->num_dwb; i++) { in dcn302_resource_destruct() 1083 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) { in dcn302_resource_destruct() 1205 pool->res_cap = &res_cap_dcn302; in dcn302_resource_construct() 1213 pool->pipe_count = pool->res_cap->num_timing_generator; in dcn302_resource_construct() [all …]
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn303/ |
H A D | dcn303_resource.c | 651 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn303_dwbc_create() 686 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn303_mmhubbub_create() 930 for (i = 0; i < pool->res_cap->num_dsc; i++) { in dcn303_resource_destruct() 960 for (i = 0; i < pool->res_cap->num_ddc; i++) { in dcn303_resource_destruct() 973 for (i = 0; i < pool->res_cap->num_opp; i++) { in dcn303_resource_destruct() 978 for (i = 0; i < pool->res_cap->num_timing_generator; i++) { in dcn303_resource_destruct() 985 for (i = 0; i < pool->res_cap->num_dwb; i++) { in dcn303_resource_destruct() 1009 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) { in dcn303_resource_destruct() 1128 pool->res_cap = &res_cap_dcn303; in dcn303_resource_construct() 1136 pool->pipe_count = pool->res_cap->num_timing_generator; in dcn303_resource_construct() [all …]
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn301/ |
H A D | dcn301_resource.c | 1052 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn301_destruct() 1082 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn301_destruct() 1095 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn301_destruct() 1100 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn301_destruct() 1107 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn301_destruct() 1130 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { in dcn301_destruct() 1146 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn301_destruct() 1175 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn301_dwbc_create() 1200 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn301_mmhubbub_create() 1299 loaded_ip->max_num_otg = pool->base.res_cap->num_timing_generator; in init_soc_bounding_box() [all …]
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn316/ |
H A D | dcn316_resource.c | 1112 if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) in dcn31_link_enc_create_minimal() 1382 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn316_resource_destruct() 1412 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn316_resource_destruct() 1425 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn316_resource_destruct() 1430 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn316_resource_destruct() 1437 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn316_resource_destruct() 1460 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { in dcn316_resource_destruct() 1476 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn316_resource_destruct() 1510 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_dwbc_create() 1535 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_mmhubbub_create() [all …]
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn315/ |
H A D | dcn315_resource.c | 1116 if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) in dcn31_link_enc_create_minimal() 1384 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn315_resource_destruct() 1414 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn315_resource_destruct() 1427 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn315_resource_destruct() 1432 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn315_resource_destruct() 1439 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn315_resource_destruct() 1462 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { in dcn315_resource_destruct() 1478 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn315_resource_destruct() 1512 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_dwbc_create() 1537 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_mmhubbub_create() [all …]
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn314/ |
H A D | dcn314_resource.c | 1190 if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) in dcn31_link_enc_create_minimal() 1457 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn314_resource_destruct() 1486 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn314_resource_destruct() 1499 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn314_resource_destruct() 1504 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn314_resource_destruct() 1511 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn314_resource_destruct() 1534 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { in dcn314_resource_destruct() 1550 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn314_resource_destruct() 1587 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_dwbc_create() 1612 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_mmhubbub_create() [all …]
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn31/ |
H A D | dcn31_resource.c | 1118 if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) in dcn31_link_enc_create_minimal() 1384 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn31_resource_destruct() 1414 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn31_resource_destruct() 1427 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn31_resource_destruct() 1432 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn31_resource_destruct() 1439 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn31_resource_destruct() 1462 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { in dcn31_resource_destruct() 1478 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn31_resource_destruct() 1515 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_dwbc_create() 1540 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_mmhubbub_create() [all …]
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn321/ |
H A D | dcn321_resource.c | 1370 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn321_resource_destruct() 1399 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn321_resource_destruct() 1412 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn321_resource_destruct() 1417 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn321_resource_destruct() 1424 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn321_resource_destruct() 1447 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { in dcn321_resource_destruct() 1463 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn321_resource_destruct() 1485 uint32_t dwb_count = pool->res_cap->num_dwb; in dcn321_dwbc_create() 1514 uint32_t dwb_count = pool->res_cap->num_dwb; in dcn321_mmhubbub_create() 1659 pool->base.res_cap = &res_cap_dcn321; in dcn321_resource_construct() [all …]
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn30/ |
H A D | dcn30_resource.c | 1082 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn30_resource_destruct() 1112 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn30_resource_destruct() 1125 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn30_resource_destruct() 1130 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn30_resource_destruct() 1137 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn30_resource_destruct() 1160 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { in dcn30_resource_destruct() 1216 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn30_dwbc_create() 1241 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn30_mmhubbub_create() 1444 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) { in dcn30_acquire_post_bldn_3dlut() 1474 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) { in dcn30_release_post_bldn_3dlut() [all …]
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/dce80/ |
H A D | dce80_resource.c | 375 static const struct resource_caps res_cap = { variable 829 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce80_resource_destruct() 959 pool->base.res_cap = &res_cap; in dce80_construct() 967 pool->base.pipe_count = res_cap.num_timing_generator; in dce80_construct() 968 pool->base.timing_generator_count = res_cap.num_timing_generator; in dce80_construct() 1087 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce80_construct() 1161 pool->base.res_cap = &res_cap_81; in dce81_construct() 1287 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce81_construct() 1361 pool->base.res_cap = &res_cap_83; in dce83_construct() 1484 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce83_construct()
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/dce60/ |
H A D | dce60_resource.c | 372 static const struct resource_caps res_cap = { variable 822 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce60_resource_destruct() 952 pool->base.res_cap = &res_cap; in dce60_construct() 960 pool->base.pipe_count = res_cap.num_timing_generator; in dce60_construct() 961 pool->base.timing_generator_count = res_cap.num_timing_generator; in dce60_construct() 1073 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce60_construct() 1147 pool->base.res_cap = &res_cap_61; in dce61_construct() 1271 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce61_construct() 1345 pool->base.res_cap = &res_cap_64; in dce64_construct() 1465 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce64_construct()
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn32/ |
H A D | dcn32_resource.c | 1384 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn32_resource_destruct() 1414 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn32_resource_destruct() 1427 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn32_resource_destruct() 1432 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn32_resource_destruct() 1439 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn32_resource_destruct() 1462 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { in dcn32_resource_destruct() 1478 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn32_resource_destruct() 1500 uint32_t dwb_count = pool->res_cap->num_dwb; in dcn32_dwbc_create() 1529 uint32_t dwb_count = pool->res_cap->num_dwb; in dcn32_mmhubbub_create() 1620 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) { in dcn32_release_post_bldn_3dlut() [all …]
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H A D | dcn32_hwseq.c | 1447 for (i = 0; i < dc->res_pool->res_cap->num_dsc; i++) { in dcn32_update_dsc_pg() 1525 if (opp_id_src0 >= dc->res_pool->res_cap->num_opp) { in dcn32_init_blank() 1530 for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) { in dcn32_init_blank() 1540 if (opp_id_src1 >= dc->res_pool->res_cap->num_opp) { in dcn32_init_blank() 1544 for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) { in dcn32_init_blank() 1604 ASSERT(opp_id_src0 < dc->res_pool->res_cap->num_opp); in dcn32_blank_phantom() 1606 for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) { in dcn32_blank_phantom()
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/dce100/ |
H A D | dce100_resource.c | 374 static const struct resource_caps res_cap = { variable 781 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce100_resource_destruct() 993 pool->base.res_cap = &res_cap; in dce100_resource_construct() 1068 pool->base.pipe_count = res_cap.num_timing_generator; in dce100_resource_construct() 1069 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; in dce100_resource_construct() 1125 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce100_resource_construct()
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/core/ |
H A D | dc_link_enc_cfg.c | 40 for (i = 0; i < stream->ctx->dc->res_pool->res_cap->num_dig_link_enc; i++) { in is_dig_link_enc_stream() 180 for (i = 0; i < ctx->dc->res_pool->res_cap->num_dig_link_enc; i++) { in find_first_avail_link_enc() 189 for (i = 0; i < ctx->dc->res_pool->res_cap->num_dig_link_enc; i++) { in find_first_avail_link_enc() 272 for (i = 0; i < dc->res_pool->res_cap->num_dig_link_enc; i++) { in clear_enc_assignments() 547 for (i = 0; i < dc->res_pool->res_cap->num_dig_link_enc; i++) { in link_enc_cfg_get_next_avail_link_enc() 711 for (j = 0; j < dc->res_pool->res_cap->num_dig_link_enc; j++) { in link_enc_cfg_validate()
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn20/ |
H A D | dcn20_resource.c | 1096 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn20_resource_destruct() 1126 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn20_resource_destruct() 1139 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn20_resource_destruct() 1144 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn20_resource_destruct() 1151 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn20_resource_destruct() 1322 if (pool->res_cap->num_dsc == pool->res_cap->num_opp) { in dcn20_acquire_dsc() 1336 for (i = 0; i < pool->res_cap->num_dsc; i++) in dcn20_acquire_dsc() 1350 for (i = 0; i < pool->res_cap->num_dsc; i++) in dcn20_release_dsc() 2234 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn20_dwbc_create() 2257 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn20_mmhubbub_create() [all …]
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn21/ |
H A D | dcn21_resource.c | 690 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn21_resource_destruct() 720 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn21_resource_destruct() 733 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn21_resource_destruct() 738 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn21_resource_destruct() 745 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn21_resource_destruct() 1414 pool->base.res_cap = &res_cap_rn; in dcn21_resource_construct() 1418 pool->base.res_cap = &res_cap_rn_FPGA_4pipe; in dcn21_resource_construct() 1429 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dcn21_resource_construct() 1642 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn21_resource_construct() 1678 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn21_resource_construct()
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/dce120/ |
H A D | dce120_resource.c | 497 static const struct resource_caps res_cap = { variable 625 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce120_resource_destruct() 1067 pool->base.res_cap = &res_cap; in dce120_resource_construct() 1071 pool->base.pipe_count = res_cap.num_timing_generator; in dce120_resource_construct() 1072 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; in dce120_resource_construct() 1217 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce120_resource_construct()
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn201/ |
H A D | dcn201_resource.c | 945 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn201_resource_destruct() 950 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn201_resource_destruct() 1090 pool->base.res_cap = &res_cap_dnc201; in dcn201_resource_construct() 1188 dcn201_ip.max_num_otg = pool->base.res_cap->num_timing_generator; in dcn201_resource_construct() 1223 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn201_resource_construct() 1232 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn201_resource_construct() 1248 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn201_resource_construct()
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H A D | dcn201_hwseq.c | 183 ASSERT(opp_id_src0 < dc->res_pool->res_cap->num_opp); in dcn201_init_blank() 294 for (i = 0; i < res_pool->res_cap->num_opp; i++) { in dcn201_init_hw() 327 for (i = 0; i < res_pool->res_cap->num_dwb; i++) in dcn201_init_hw()
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn10/ |
H A D | dcn10_resource.c | 485 static const struct resource_caps res_cap = { variable 951 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn10_resource_destruct() 1322 pool->base.res_cap = &rv2_res_cap; in dcn10_resource_construct() 1324 pool->base.res_cap = &res_cap; in dcn10_resource_construct() 1338 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dcn10_resource_construct() 1606 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn10_resource_construct()
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/dce112/ |
H A D | dce112_resource.c | 802 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce112_resource_destruct() 1232 pool->base.res_cap = dce112_resource_cap(&ctx->asic_id); in dce112_resource_construct() 1239 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dce112_resource_construct() 1240 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; in dce112_resource_construct() 1374 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce112_resource_construct()
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/dce110/ |
H A D | dce110_resource.c | 837 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce110_resource_destruct() 1360 pool->base.res_cap = dce110_resource_cap(&ctx->asic_id); in dce110_resource_construct() 1367 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dce110_resource_construct() 1369 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; in dce110_resource_construct() 1485 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce110_resource_construct()
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
H A D | dcn31_fpu.c | 595 dcn3_1_ip.max_num_otg = dc->res_pool->res_cap->num_timing_generator; in dcn31_update_bw_bounding_box() 667 dcn3_15_ip.max_num_otg = dc->res_pool->res_cap->num_timing_generator; in dcn315_update_bw_bounding_box() 734 dcn3_16_ip.max_num_otg = dc->res_pool->res_cap->num_timing_generator; in dcn316_update_bw_bounding_box()
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/inc/ |
H A D | core_types.h | 289 const struct resource_caps *res_cap; member
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