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Searched refs:regmap_set_bits (Results 1 – 25 of 79) sorted by relevance

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/openbmc/linux/drivers/pmdomain/imx/
H A Dimx8mp-blk-ctrl.c179 regmap_set_bits(bc->regmap, GPR_REG0, USB_CLOCK_MODULE_EN); in imx8mp_hsio_blk_ctrl_power_on()
182 regmap_set_bits(bc->regmap, GPR_REG0, PCIE_CLOCK_MODULE_EN); in imx8mp_hsio_blk_ctrl_power_on()
185 regmap_set_bits(bc->regmap, GPR_REG0, in imx8mp_hsio_blk_ctrl_power_on()
230 regmap_set_bits(bc->regmap, GPR_REG0, USB_CLOCK_MODULE_EN); in imx8mp_hsio_power_notifier()
243 regmap_set_bits(bc->regmap, GPR_REG0, USB_CLOCK_MODULE_EN); in imx8mp_hsio_power_notifier()
310 regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL0, BIT(9)); in imx8mp_hdmi_blk_ctrl_power_on()
311 regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(16)); in imx8mp_hdmi_blk_ctrl_power_on()
314 regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL0, in imx8mp_hdmi_blk_ctrl_power_on()
317 regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(11)); in imx8mp_hdmi_blk_ctrl_power_on()
318 regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0, in imx8mp_hdmi_blk_ctrl_power_on()
[all …]
H A Dimx8m-blk-ctrl.c111 regmap_set_bits(bc->regmap, BLK_CLK_EN, data->clk_mask); in imx8m_blk_ctrl_power_on()
124 regmap_set_bits(bc->regmap, BLK_SFT_RSTN, data->rst_mask); in imx8m_blk_ctrl_power_on()
126 regmap_set_bits(bc->regmap, BLK_MIPI_RESET_DIV, data->mipi_phy_rst_mask); in imx8m_blk_ctrl_power_on()
429 regmap_set_bits(bc->regmap, BLK_CLK_EN, BIT(0) | BIT(1) | BIT(2)); in imx8mm_vpu_power_notifier()
440 regmap_set_bits(bc->regmap, 0x8, 0xffffffff); in imx8mm_vpu_power_notifier()
441 regmap_set_bits(bc->regmap, 0xc, 0xffffffff); in imx8mm_vpu_power_notifier()
442 regmap_set_bits(bc->regmap, 0x10, 0xffffffff); in imx8mm_vpu_power_notifier()
443 regmap_set_bits(bc->regmap, 0x14, 0xffffffff); in imx8mm_vpu_power_notifier()
533 regmap_set_bits(bc->regmap, BLK_CLK_EN, BIT(12)); in imx8mm_disp_power_notifier()
534 regmap_set_bits(bc->regmap, BLK_SFT_RSTN, BIT(6)); in imx8mm_disp_power_notifier()
[all …]
/openbmc/linux/sound/soc/codecs/
H A Djz4770.c204 regmap_set_bits(regmap, JZ4770_CODEC_REG_CR_VIC, in jz4770_codec_set_bias_level()
206 regmap_set_bits(regmap, JZ4770_CODEC_REG_CR_VIC, in jz4770_codec_set_bias_level()
298 regmap_set_bits(jz_codec->regmap, JZ4770_CODEC_REG_IFR, in jz4770_codec_mute_stream()
400 regmap_set_bits(jz_codec->regmap, JZ4770_CODEC_REG_IFR, in hpout_event()
407 regmap_set_bits(jz_codec->regmap, JZ4770_CODEC_REG_CR_HP, in hpout_event()
420 regmap_set_bits(jz_codec->regmap, JZ4770_CODEC_REG_IFR, in hpout_event()
609 regmap_set_bits(regmap, JZ4770_CODEC_REG_CR_HP, REG_CR_HP_SEL_MASK); in jz4770_codec_codec_init_regs()
612 regmap_set_bits(regmap, JZ4770_CODEC_REG_CR_LO, REG_CR_LO_SEL_MASK); in jz4770_codec_codec_init_regs()
623 regmap_set_bits(regmap, JZ4770_CODEC_REG_AICR_ADC, in jz4770_codec_codec_init_regs()
625 regmap_set_bits(regmap, JZ4770_CODEC_REG_AICR_DAC, in jz4770_codec_codec_init_regs()
[all …]
H A Djz4760.c186 regmap_set_bits(regmap, JZ4760_CODEC_REG_PMR1, REG_PMR1_SB_SLEEP); in jz4760_codec_set_bias_level()
187 regmap_set_bits(regmap, JZ4760_CODEC_REG_PMR1, REG_PMR1_SB); in jz4760_codec_set_bias_level()
377 regmap_set_bits(jz_codec->regmap, JZ4760_CODEC_REG_IFR, in hpout_event()
384 regmap_set_bits(jz_codec->regmap, JZ4760_CODEC_REG_CR1, in hpout_event()
397 regmap_set_bits(jz_codec->regmap, JZ4760_CODEC_REG_IFR, in hpout_event()
582 regmap_set_bits(regmap, JZ4760_CODEC_REG_CR1, REG_CR1_OUTSEL_MASK); in jz4760_codec_codec_init_regs()
593 regmap_set_bits(regmap, JZ4760_CODEC_REG_AICR, in jz4760_codec_codec_init_regs()
611 regmap_set_bits(jz_codec->regmap, JZ4760_CODEC_REG_CR2, in jz4760_codec_codec_init_regs()
H A Djz4740.c222 regmap_set_bits(regmap, JZ4740_REG_CODEC_1, JZ4740_CODEC_1_RESET); in jz4740_codec_wakeup()
257 regmap_set_bits(regmap, JZ4740_REG_CODEC_1, mask); in jz4740_codec_set_bias_level()
261 regmap_set_bits(regmap, JZ4740_REG_CODEC_1, mask); in jz4740_codec_set_bias_level()
H A Dcs35l45.c132 regmap_set_bits(cs35l45->regmap, CS35L45_PWRMGT_CTL, in cs35l45_dsp_preload_ev()
465 regmap_set_bits(cs35l45->regmap, CS35L45_REFCLK_INPUT, CS35L45_PLL_OPEN_LOOP_MASK); in cs35l45_set_pll()
471 regmap_set_bits(cs35l45->regmap, CS35L45_REFCLK_INPUT, CS35L45_PLL_REFCLK_EN_MASK); in cs35l45_set_pll()
762 regmap_set_bits(cs35l45->regmap, CS35L45_WAKESRC_CTL, in cs35l45_setup_hibernate()
768 regmap_set_bits(cs35l45->regmap, CS35L45_WKI2C_CTL, in cs35l45_setup_hibernate()
778 regmap_set_bits(cs35l45->regmap, CS35L45_IRQ1_MASK_2, CS35L45_DSP_VIRT2_MBOX_MASK); in cs35l45_enter_hibernate()
856 regmap_set_bits(cs35l45->regmap, CS35L45_ERROR_RELEASE, CS35L45_GLOBAL_ERR_RLS_MASK); in cs35l45_runtime_resume()
/openbmc/linux/drivers/pwm/
H A Dpwm-stm32.c118 regmap_set_bits(priv->regmap, TIM_EGR, TIM_EGR_UG); in stm32_pwm_raw_capture()
119 regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN); in stm32_pwm_raw_capture()
125 regmap_set_bits(priv->regmap, TIM_CCER, ccen); in stm32_pwm_raw_capture()
369 regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE); in stm32_pwm_config()
387 regmap_set_bits(priv->regmap, TIM_BDTR, TIM_BDTR_MOE); in stm32_pwm_config()
421 regmap_set_bits(priv->regmap, TIM_CCER, mask); in stm32_pwm_enable()
424 regmap_set_bits(priv->regmap, TIM_EGR, TIM_EGR_UG); in stm32_pwm_enable()
427 regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN); in stm32_pwm_enable()
579 regmap_set_bits(priv->regmap, TIM_CCER, TIM_CCER_CC1NE); in stm32_pwm_detect_complementary()
596 regmap_set_bits(priv->regmap, TIM_CCER, TIM_CCER_CCXE); in stm32_pwm_detect_channels()
H A Dpwm-fsl-ftm.c67 regmap_set_bits(fpc->regmap, FTM_MODE, FTM_MODE_WPDIS); in ftm_clear_write_protection()
72 regmap_set_bits(fpc->regmap, FTM_FMS, FTM_FMS_WPEN); in ftm_set_write_protection()
95 regmap_set_bits(fpc->regmap, FTM_SC, BIT(pwm->hwpwm + 16)); in fsl_pwm_request()
316 regmap_set_bits(fpc->regmap, FTM_OUTMASK, in fsl_pwm_apply()
H A Dpwm-jz4740.c92 regmap_set_bits(jz->map, TCU_REG_TCSRc(pwm->hwpwm), TCU_TCSR_PWM_EN); in jz4740_pwm_enable()
186 regmap_set_bits(jz4740->map, TCU_REG_TCSRc(pwm->hwpwm), in jz4740_pwm_apply()
/openbmc/linux/drivers/misc/
H A Dtps6594-pfsm.c113 ret = regmap_set_bits(regmap, TPS6594_REG_FSM_I2C_TRIGGERS, in tps6594_pfsm_configure_ret_trig()
122 ret = regmap_set_bits(regmap, TPS6594_REG_FSM_I2C_TRIGGERS, in tps6594_pfsm_configure_ret_trig()
152 ret = regmap_set_bits(pfsm->regmap, TPS6594_REG_RTC_CTRL_2, in tps6594_pfsm_ioctl()
168 ret = regmap_set_bits(pfsm->regmap, TPS6594_REG_FSM_NSLEEP_TRIGGERS, in tps6594_pfsm_ioctl()
187 ret = regmap_set_bits(pfsm->regmap, TPS6594_REG_FSM_NSLEEP_TRIGGERS, in tps6594_pfsm_ioctl()
H A Dtps6594-esm.c68 ret = regmap_set_bits(tps->regmap, TPS6594_REG_ESM_SOC_MODE_CFG, in tps6594_esm_probe()
73 ret = regmap_set_bits(tps->regmap, TPS6594_REG_ESM_SOC_START_REG, in tps6594_esm_probe()
126 return regmap_set_bits(tps->regmap, TPS6594_REG_ESM_SOC_START_REG, in tps6594_esm_resume()
/openbmc/linux/drivers/pmdomain/mediatek/
H A Dmtk-pm-domains.c93 regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_SRAM_ISOINT_B_BIT); in scpsys_sram_enable()
108 regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_SRAM_CLKISO_BIT); in scpsys_sram_disable()
113 regmap_set_bits(scpsys->base, pd->data->ctl_offs, pd->data->sram_pdn_bits); in scpsys_sram_disable()
132 regmap_set_bits(regmap, bpd[i].bus_prot_set, mask); in _scpsys_bus_protect_enable()
227 regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_ON_BIT); in scpsys_power_on()
228 regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_ON_2ND_BIT); in scpsys_power_on()
238 regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_RST_B_BIT); in scpsys_power_on()
281 regmap_set_bits(scpsys->base, pd->data->ext_buck_iso_offs, in scpsys_power_off()
287 regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_ISO_BIT); in scpsys_power_off()
288 regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_CLK_DIS_BIT); in scpsys_power_off()
/openbmc/linux/drivers/mfd/
H A Dtps65910.c317 ret = regmap_set_bits(tps65910->regmap, TPS65910_DEVCTRL, in tps65910_sleepinit()
325 ret = regmap_set_bits(tps65910->regmap, in tps65910_sleepinit()
335 ret = regmap_set_bits(tps65910->regmap, in tps65910_sleepinit()
345 ret = regmap_set_bits(tps65910->regmap, in tps65910_sleepinit()
503 ret = regmap_set_bits(tps65910->regmap, TPS65910_DEVCTRL, in tps65910_i2c_probe()
/openbmc/linux/sound/soc/fsl/
H A Dfsl_micfil.c459 ret = regmap_set_bits(micfil->regmap, REG_MICFIL_CTRL1, in fsl_micfil_reset()
558 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG, in fsl_micfil_init_hwvad_energy_mode()
580 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL2, in fsl_micfil_init_hwvad_envelope_mode()
584 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL2, in fsl_micfil_init_hwvad_envelope_mode()
588 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_SCONFIG, in fsl_micfil_init_hwvad_envelope_mode()
592 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_SCONFIG, in fsl_micfil_init_hwvad_envelope_mode()
600 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG, in fsl_micfil_init_hwvad_envelope_mode()
604 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG, in fsl_micfil_init_hwvad_envelope_mode()
608 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_NCONFIG, in fsl_micfil_init_hwvad_envelope_mode()
642 regmap_set_bits(micfil->regmap, REG_MICFIL_VAD0_CTRL1, in fsl_micfil_hwvad_enable()
[all …]
/openbmc/linux/drivers/gpio/
H A Dgpio-tps65910.c46 regmap_set_bits(tps65910->regmap, TPS65910_GPIO0 + offset, in tps65910_gpio_set()
62 return regmap_set_bits(tps65910->regmap, TPS65910_GPIO0 + offset, in tps65910_gpio_output()
160 ret = regmap_set_bits(tps65910->regmap, in tps65910_gpio_probe()
/openbmc/linux/sound/soc/jz4740/
H A Djz4740-i2s.c107 regmap_set_bits(i2s->regmap, JZ_REG_AIC_CTRL, JZ_AIC_CTRL_TFLUSH); in jz4740_i2s_startup()
109 regmap_set_bits(i2s->regmap, JZ_REG_AIC_CTRL, JZ_AIC_CTRL_RFLUSH); in jz4740_i2s_startup()
122 regmap_set_bits(i2s->regmap, JZ_REG_AIC_CTRL, JZ_AIC_CTRL_TFLUSH); in jz4740_i2s_startup()
128 regmap_set_bits(i2s->regmap, JZ_REG_AIC_CONF, JZ_AIC_CONF_ENABLE); in jz4740_i2s_startup()
160 regmap_set_bits(i2s->regmap, JZ_REG_AIC_CTRL, mask); in jz4740_i2s_trigger()
448 regmap_set_bits(i2s->regmap, JZ_REG_AIC_CONF, JZ_AIC_CONF_ENABLE); in jz4740_i2s_resume()
/openbmc/linux/drivers/iio/adc/
H A Dadi-axi-adc.c69 ret = regmap_set_bits(st->regmap, ADI_AXI_REG_RSTN, in axi_adc_enable()
75 return regmap_set_bits(st->regmap, ADI_AXI_REG_RSTN, in axi_adc_enable()
111 return regmap_set_bits(st->regmap, ADI_AXI_REG_CHAN_CTRL(chan), in axi_adc_chan_enable()
/openbmc/linux/drivers/net/pcs/
H A Dpcs-mtk-lynxi.c146 regmap_set_bits(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, in mtk_pcs_lynxi_config()
150 regmap_set_bits(mpcs->regmap, SGMSYS_RESERVED_0, in mtk_pcs_lynxi_config()
207 regmap_set_bits(mpcs->regmap, SGMSYS_PCS_CONTROL_1, BMCR_ANRESTART); in mtk_pcs_lynxi_restart_an()
/openbmc/linux/drivers/soc/qcom/
H A Dramp_controller.c82 ret = regmap_set_bits(r, d->cmd_reg, RC_ROOT_EN); in rc_wait_for_update()
108 ret = regmap_set_bits(r, d->cmd_reg + RC_REG_CFG_UPDATE, ce); in rc_set_cfg_update()
113 ret = regmap_set_bits(r, d->cmd_reg + RC_REG_CFG_UPDATE, RC_CFG_UPDATE_EN); in rc_set_cfg_update()
/openbmc/linux/drivers/hwmon/
H A Dmax31760.c270 return regmap_set_bits(state->regmap, REG_CR3, BIT(channel)); in max31760_write()
285 return regmap_set_bits(state->regmap, REG_CR2, CR2_DFC); in max31760_write()
477 ret = regmap_set_bits(state->regmap, REG_CR1, CR1_HYST); in pwm1_auto_point_temp_hyst_store()
537 ret = regmap_set_bits(state->regmap, REG_CR2, CR2_ALERTS); in max31760_probe()
567 return regmap_set_bits(state->regmap, REG_CR2, CR2_STBY); in max31760_suspend()
/openbmc/linux/sound/soc/mediatek/mt8188/
H A Dmt8188-dai-adda.c125 regmap_set_bits(afe->regmap, AFE_ADDA_MTKAIF_CFG0, in mt8188_adda_mtkaif_init()
128 regmap_set_bits(afe->regmap, AFE_AUD_PAD_TOP, RG_RX_PROTOCOL2); in mt8188_adda_mtkaif_init()
211 regmap_set_bits(afe->regmap, reg, val); in mtk_adda_ul_mictype()
463 regmap_set_bits(afe->regmap, AFE_ADDA_DL_SDM_DCCOMP_CON, in mtk_dai_da_configure()
/openbmc/linux/drivers/gpu/drm/ingenic/
H A Dingenic-ipu.c357 regmap_set_bits(ipu->map, JZ_REG_IPU_CTRL, JZ_IPU_CTRL_RST); in ingenic_ipu_plane_atomic_update()
360 regmap_set_bits(ipu->map, JZ_REG_IPU_CTRL, in ingenic_ipu_plane_atomic_update()
385 regmap_set_bits(ipu->map, JZ_REG_IPU_CTRL, JZ_IPU_CTRL_SPKG_SEL); in ingenic_ipu_plane_atomic_update()
479 regmap_set_bits(ipu->map, JZ_REG_IPU_CTRL, JZ_IPU_CTRL_CSC_EN); in ingenic_ipu_plane_atomic_update()
557 regmap_set_bits(ipu->map, JZ_REG_IPU_CTRL, in ingenic_ipu_plane_atomic_update()
660 regmap_set_bits(ipu->map, JZ_REG_IPU_CTRL, JZ_IPU_CTRL_STOP); in ingenic_ipu_plane_atomic_disable()
778 regmap_set_bits(ipu->map, JZ_REG_IPU_CTRL, JZ_IPU_CTRL_RUN); in ingenic_ipu_irq_handler()
/openbmc/linux/drivers/iio/accel/
H A Dkionix-kx022a.c335 ret = regmap_set_bits(data->regmap, KX022A_REG_CNTL, in kx022a_turn_on_off_unlocked()
740 return regmap_set_bits(data->regmap, KX022A_REG_CNTL, in kx022a_set_drdy_irq()
763 return regmap_set_bits(data->regmap, data->ien_reg, mask); in kx022a_prepare_irq_pin()
819 ret = regmap_set_bits(data->regmap, KX022A_REG_BUF_CNTL2, in kx022a_fifo_enable()
825 ret = regmap_set_bits(data->regmap, data->ien_reg, in kx022a_fifo_enable()
993 ret = regmap_set_bits(data->regmap, KX022A_REG_BUF_CNTL2, in kx022a_chip_init()
/openbmc/linux/drivers/leds/
H A Dleds-mt6323.c412 ret = regmap_set_bits(regmap, regs->iwled_en_ctrl, BIT(led->id)); in mtk_wled_hw_on()
416 ret = regmap_set_bits(regmap, regs->iwled_en_ctrl, BIT(led->id + 1)); in mtk_wled_hw_on()
439 ret = regmap_set_bits(regmap, regs->top_ckpdn[0], RG_VWLED_32K_CK_PDN); in mtk_wled_hw_off()
443 ret = regmap_set_bits(regmap, regs->top_ckpdn[0], RG_VWLED_6M_CK_PDN); in mtk_wled_hw_off()
447 ret = regmap_set_bits(regmap, regs->top_ckpdn[0], RG_VWLED_1M_CK_PDN); in mtk_wled_hw_off()
/openbmc/linux/drivers/soc/mediatek/
H A Dmtk-infracfg.c89 regmap_set_bits(infracfg, MT8192_INFRA_CTRL, in mtk_infracfg_init()

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