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Searched refs:reg_name (Results 1 – 25 of 271) sorted by relevance

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/openbmc/linux/drivers/gpu/drm/amd/display/dmub/src/
H A Ddmub_reg.h37 #define REG_OFFSET(reg_name) (BASE(mm##reg_name##_BASE_IDX) + mm##reg_name) argument
39 #define FD_SHIFT(reg_name, field) reg_name##__##field##__SHIFT argument
41 #define FD_MASK(reg_name, field) reg_name##__##field##_MASK argument
47 #define FN(reg_name, field) FD(reg_name##__##field) argument
58 #define REG_SET_N(reg_name, n, initial_val, ...) \ argument
59 dmub_reg_set(CTX, REG(reg_name), initial_val, n, __VA_ARGS__)
61 #define REG_SET(reg_name, initial_val, field, val) \ argument
62 REG_SET_N(reg_name, 1, initial_val, \
63 FN(reg_name, field), val)
85 #define REG_UPDATE_N(reg_name, n, ...)\ argument
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/inc/
H A Dreg_helper.h39 #define REG_READ(reg_name) \ argument
40 dm_read_reg(CTX, REG(reg_name))
42 #define REG_WRITE(reg_name, value) \ argument
43 dm_write_reg(CTX, REG(reg_name), value)
54 #define REG_SET_N(reg_name, n, initial_val, ...) \ argument
56 REG(reg_name), \
60 #define FN(reg_name, field) \ argument
61 FD(reg_name##__##field)
63 #define REG_SET(reg_name, initial_val, field, val) \ argument
64 REG_SET_N(reg_name, 1, initial_val, \
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/openbmc/linux/tools/perf/util/
H A Dperf_regs.c28 const char *reg_name = NULL; in perf_reg_name() local
31 reg_name = __perf_reg_name_csky(id); in perf_reg_name()
33 reg_name = __perf_reg_name_loongarch(id); in perf_reg_name()
35 reg_name = __perf_reg_name_mips(id); in perf_reg_name()
37 reg_name = __perf_reg_name_powerpc(id); in perf_reg_name()
39 reg_name = __perf_reg_name_riscv(id); in perf_reg_name()
41 reg_name = __perf_reg_name_s390(id); in perf_reg_name()
43 reg_name = __perf_reg_name_x86(id); in perf_reg_name()
45 reg_name = __perf_reg_name_arm(id); in perf_reg_name()
47 reg_name = __perf_reg_name_arm64(id); in perf_reg_name()
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/gpio/dcn21/
H A Dhw_factory_dcn21.c57 #define REG(reg_name)\ argument
58 BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
60 #define SF_HPD(reg_name, field_name, post_fix)\ argument
61 .field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix
63 #define REGI(reg_name, block, id)\ argument
64 BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
65 mm ## block ## id ## _ ## reg_name
67 #define SF(reg_name, field_name, post_fix)\ argument
68 .field_name = reg_name ## __ ## field_name ## post_fix
99 #define SF_DDC(reg_name, field_name, post_fix)\ argument
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/
H A Ddm_services.h96 #define get_reg_field_value(reg_value, reg_name, reg_field)\ argument
99 reg_name ## __ ## reg_field ## _MASK,\
100 reg_name ## __ ## reg_field ## __SHIFT)
112 #define set_reg_field_value(reg_value, value, reg_name, reg_field)\ argument
116 reg_name ## __ ## reg_field ## _MASK,\
117 reg_name ## __ ## reg_field ## __SHIFT)
157 #define generic_reg_update_soc15(ctx, inst_offset, reg_name, n, ...)\ argument
158 …generic_reg_update_ex(ctx, DCE_BASE.instance[0].segment[mm##reg_name##_BASE_IDX] + mm##reg_name +…
161 #define generic_reg_set_soc15(ctx, inst_offset, reg_name, n, ...)\ argument
162 …generic_reg_set_ex(ctx, DCE_BASE.instance[0].segment[mm##reg_name##_BASE_IDX] + mm##reg_name + ins…
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/gpio/dce120/
H A Dhw_factory_dce120.c46 #define SF_HPD(reg_name, field_name, post_fix)\ argument
47 .field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix
50 #define SF_HPD(reg_name, field_name, post_fix)\ argument
51 .field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix
60 #define REG(reg_name)\ argument
61 BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
63 #define REGI(reg_name, block, id)\ argument
64 BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
65 mm ## block ## id ## _ ## reg_name
96 #define SF_DDC(reg_name, field_name, post_fix)\ argument
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/gpio/dcn20/
H A Dhw_factory_dcn20.c59 #define REG(reg_name)\ argument
60 BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
62 #define SF_HPD(reg_name, field_name, post_fix)\ argument
63 .field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix
65 #define REGI(reg_name, block, id)\ argument
66 BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
67 mm ## block ## id ## _ ## reg_name
69 #define SF(reg_name, field_name, post_fix)\ argument
70 .field_name = reg_name ## __ ## field_name ## post_fix
102 #define SF_DDC(reg_name, field_name, post_fix)\ argument
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/gpio/dcn30/
H A Dhw_factory_dcn30.c66 #define REG(reg_name)\ argument
67 BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
69 #define SF_HPD(reg_name, field_name, post_fix)\ argument
70 .field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix
72 #define REGI(reg_name, block, id)\ argument
73 BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
74 mm ## block ## id ## _ ## reg_name
76 #define SF(reg_name, field_name, post_fix)\ argument
77 .field_name = reg_name ## __ ## field_name ## post_fix
109 #define SF_DDC(reg_name, field_name, post_fix)\ argument
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/gpio/dcn315/
H A Dhw_factory_dcn315.c63 #define REG(reg_name)\ argument
64 BASE(reg ## reg_name ## _BASE_IDX) + reg ## reg_name
66 #define SF_HPD(reg_name, field_name, post_fix)\ argument
67 .field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix
69 #define REGI(reg_name, block, id)\ argument
70 BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
71 reg ## block ## id ## _ ## reg_name
73 #define SF(reg_name, field_name, post_fix)\ argument
74 .field_name = reg_name ## __ ## field_name ## post_fix
105 #define SF_DDC(reg_name, field_name, post_fix)\ argument
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/gpio/dcn32/
H A Dhw_factory_dcn32.c59 #define REG(reg_name)\ argument
60 BASE(reg ## reg_name ## _BASE_IDX) + reg ## reg_name
62 #define SF_HPD(reg_name, field_name, post_fix)\ argument
63 .field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix
65 #define REGI(reg_name, block, id)\ argument
66 BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
67 reg ## block ## id ## _ ## reg_name
69 #define SF(reg_name, field_name, post_fix)\ argument
70 .field_name = reg_name ## __ ## field_name ## post_fix
101 #define SF_DDC(reg_name, field_name, post_fix)\ argument
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/gpio/dcn10/
H A Dhw_factory_dcn10.c47 #define SF_HPD(reg_name, field_name, post_fix)\ argument
48 .field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix
57 #define REG(reg_name)\ argument
58 BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
60 #define REGI(reg_name, block, id)\ argument
61 BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
62 mm ## block ## id ## _ ## reg_name
92 #define SF_DDC(reg_name, field_name, post_fix)\ argument
93 .field_name = reg_name ## __ ## field_name ## post_fix
128 #define SF_GENERIC(reg_name, field_name, post_fix)\ argument
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn321/
H A Ddcn321_resource.c115 #define SR(reg_name)\ argument
116 REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
117 reg ## reg_name
118 #define SR_ARR(reg_name, id)\ argument
119 REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
120 reg ## reg_name
121 #define SR_ARR_INIT(reg_name, id, value)\ argument
122 REG_STRUCT[id].reg_name = value
124 #define SRI(reg_name, block, id)\ argument
125 REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_panel_cntl.h32 #define DCE_PANEL_CNTL_SR(reg_name, block)\ argument
33 .reg_name = mm ## block ## _ ## reg_name
45 #define DCN_PANEL_CNTL_SR(reg_name, block)\ argument
46 .reg_name = BASE(mm ## block ## _ ## reg_name ## _BASE_IDX) + \
47 mm ## block ## _ ## reg_name
59 #define DCE_PANEL_CNTL_SF(reg_name, field_name, post_fix)\ argument
60 .field_name = reg_name ## __ ## field_name ## post_fix
/openbmc/qemu/tests/tcg/hexagon/
H A Dreg_mut.c26 #define WRITE_REG_NOCLOBBER(output, reg_name, input) \ argument
27 asm volatile(reg_name " = %1\n\t" \
28 "%0 = " reg_name "\n\t" \
33 #define WRITE_REG_ENCODED(output, reg_name, input, encoding) \ argument
36 "%0 = " reg_name "\n\t" \
41 #define WRITE_REG_PAIR_ENCODED(output, reg_name, input, encoding) \ argument
44 "%0 = " reg_name "\n\t" \
/openbmc/linux/drivers/gpu/drm/amd/display/dc/gpio/dce110/
H A Dhw_factory_dce110.c42 #define SF_HPD(reg_name, field_name, post_fix)\ argument
43 .field_name = reg_name ## __ ## field_name ## post_fix
45 #define REG(reg_name)\ argument
46 mm ## reg_name
48 #define REGI(reg_name, block, id)\ argument
49 mm ## block ## id ## _ ## reg_name
79 #define SF_DDC(reg_name, field_name, post_fix)\ argument
80 .field_name = reg_name ## __ ## field_name ## post_fix
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn301/
H A Ddcn301_resource.c114 #define SR(reg_name)\ argument
115 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
116 mm ## reg_name
118 #define SRI(reg_name, block, id)\ argument
119 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
120 mm ## block ## id ## _ ## reg_name
122 #define SRI2(reg_name, block, id)\ argument
123 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
124 mm ## reg_name
126 #define SRIR(var_name, reg_name, block, id)\ argument
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/openbmc/linux/tools/testing/selftests/kvm/aarch64/
H A Ddebug-exceptions.c40 #define GEN_DEBUG_WRITE_REG(reg_name) \ argument
41 static void write_##reg_name(int num, uint64_t val) \
45 write_sysreg(val, reg_name##0_el1); \
48 write_sysreg(val, reg_name##1_el1); \
51 write_sysreg(val, reg_name##2_el1); \
54 write_sysreg(val, reg_name##3_el1); \
57 write_sysreg(val, reg_name##4_el1); \
60 write_sysreg(val, reg_name##5_el1); \
63 write_sysreg(val, reg_name##6_el1); \
66 write_sysreg(val, reg_name##7_el1); \
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/openbmc/linux/tools/lib/bpf/
H A Dusdt.c1237 static int calc_pt_regs_off(const char *reg_name) in calc_pt_regs_off() argument
1273 if (strcmp(reg_name, reg_map[i].names[j]) == 0) in calc_pt_regs_off()
1278 pr_warn("usdt: unrecognized register '%s'\n", reg_name); in calc_pt_regs_off()
1284 char reg_name[16]; in parse_usdt_arg() local
1288 if (sscanf(arg_str, " %d @ %ld ( %%%15[^)] ) %n", arg_sz, &off, reg_name, &len) == 3) { in parse_usdt_arg()
1292 reg_off = calc_pt_regs_off(reg_name); in parse_usdt_arg()
1296 } else if (sscanf(arg_str, " %d @ ( %%%15[^)] ) %n", arg_sz, reg_name, &len) == 2) { in parse_usdt_arg()
1300 reg_off = calc_pt_regs_off(reg_name); in parse_usdt_arg()
1304 } else if (sscanf(arg_str, " %d @ %%%15s %n", arg_sz, reg_name, &len) == 2) { in parse_usdt_arg()
1309 reg_off = calc_pt_regs_off(reg_name); in parse_usdt_arg()
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_dwb.h34 #define SR(reg_name)\ argument
35 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
36 mm ## reg_name
38 #define SRI(reg_name, block, id)\ argument
39 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
40 mm ## block ## id ## _ ## reg_name
43 #define SRII(reg_name, block, id)\ argument
44 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
45 mm ## block ## id ## _ ## reg_name
47 #define SF(reg_name, field_name, post_fix)\ argument
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn32/
H A Ddcn32_resource.c112 #define SR(reg_name)\ argument
113 REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
114 reg ## reg_name
115 #define SR_ARR(reg_name, id) \ argument
116 REG_STRUCT[id].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
118 #define SR_ARR_INIT(reg_name, id, value) \ argument
119 REG_STRUCT[id].reg_name = value
121 #define SRI(reg_name, block, id)\ argument
122 REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
123 reg ## block ## id ## _ ## reg_name
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn201/
H A Ddcn201_resource.c251 #define SR(reg_name)\ argument
252 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
253 mm ## reg_name
255 #define SRI(reg_name, block, id)\ argument
256 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
257 mm ## block ## id ## _ ## reg_name
259 #define SRIR(var_name, reg_name, block, id)\ argument
260 .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
261 mm ## block ## id ## _ ## reg_name
263 #define SRII(reg_name, block, id)\ argument
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/
H A Drv1_clk_mgr_clk.c43 #define CLK_REG(reg_name, block, inst)\ argument
44 CLK_BASE(mm ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \
45 mm ## block ## _ ## inst ## _ ## reg_name
47 #define REG(reg_name) \ argument
48 CLK_REG(reg_name, CLK0, 0)
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn302/
H A Ddcn302_resource.c164 #define NBIO_SR(reg_name)\ argument
165 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
166 mm ## reg_name
173 #define SR(reg_name)\ argument
174 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
176 #define SF(reg_name, field_name, post_fix)\ argument
177 .field_name = reg_name ## __ ## field_name ## post_fix
179 #define SRI(reg_name, block, id)\ argument
180 ….reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + mm ## block ## id ## _ ## reg_…
182 #define SRI2(reg_name, block, id)\ argument
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn303/
H A Ddcn303_resource.c142 #define NBIO_SR(reg_name)\ argument
143 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
144 mm ## reg_name
151 #define SR(reg_name)\ argument
152 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
154 #define SF(reg_name, field_name, post_fix)\ argument
155 .field_name = reg_name ## __ ## field_name ## post_fix
157 #define SRI(reg_name, block, id)\ argument
158 ….reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + mm ## block ## id ## _ ## reg_…
160 #define SRI2(reg_name, block, id)\ argument
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/
H A Ddcn315_smu.c63 #define REG(reg_name) \ argument
64 (MP0_BASE.instance[0].segment[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)
66 #define FN(reg_name, field) \ argument
67 FD(reg_name##__##field)
69 #define REG_NBIO(reg_name) \ argument
70 …(NBIO_BASE.instance[0].segment[regBIF_BX_PF2_ ## reg_name ## _BASE_IDX] + regBIF_BX_PF2_ ## reg_na…

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