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Searched refs:reg_entry (Results 1 – 10 of 10) sorted by relevance

/openbmc/linux/arch/powerpc/platforms/pseries/
H A Drtas-fadump.c283 rtas_fadump_read_regs(struct rtas_fadump_reg_entry *reg_entry, in rtas_fadump_read_regs() argument
288 while (be64_to_cpu(reg_entry->reg_id) != fadump_str_to_u64("CPUEND")) { in rtas_fadump_read_regs()
289 rtas_fadump_set_regval(regs, be64_to_cpu(reg_entry->reg_id), in rtas_fadump_read_regs()
290 be64_to_cpu(reg_entry->reg_value)); in rtas_fadump_read_regs()
291 reg_entry++; in rtas_fadump_read_regs()
293 reg_entry++; in rtas_fadump_read_regs()
294 return reg_entry; in rtas_fadump_read_regs()
315 struct rtas_fadump_reg_entry *reg_entry; in rtas_fadump_build_cpu_notes() local
340 reg_entry = (struct rtas_fadump_reg_entry *)vaddr; in rtas_fadump_build_cpu_notes()
352 if (be64_to_cpu(reg_entry->reg_id) != in rtas_fadump_build_cpu_notes()
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H A Drtas-fadump.h104 #define RTAS_FADUMP_SKIP_TO_NEXT_CPU(reg_entry) \ argument
106 while (be64_to_cpu(reg_entry->reg_id) != \
108 reg_entry++; \
109 reg_entry++; \
/openbmc/linux/arch/powerpc/platforms/powernv/
H A Dopal-fadump.h129 struct hdat_fadump_reg_entry *reg_entry; in opal_fadump_read_regs() local
136 reg_entry = (struct hdat_fadump_reg_entry *)bufp; in opal_fadump_read_regs()
137 val = (cpu_endian ? be64_to_cpu(reg_entry->reg_val) : in opal_fadump_read_regs()
138 (u64)(reg_entry->reg_val)); in opal_fadump_read_regs()
140 be32_to_cpu(reg_entry->reg_type), in opal_fadump_read_regs()
141 be32_to_cpu(reg_entry->reg_num), in opal_fadump_read_regs()
/openbmc/qemu/hw/xen/
H A Dxen_pt.c147 XenPTReg *reg_entry = NULL; in xen_pt_pci_read_config() local
187 reg_entry = xen_pt_find_reg(reg_grp_entry, find_addr); in xen_pt_pci_read_config()
188 if (reg_entry) { in xen_pt_pci_read_config()
189 XenPTRegInfo *reg = reg_entry->reg; in xen_pt_pci_read_config()
201 rc = reg->u.b.read(s, reg_entry, ptr_val, valid_mask); in xen_pt_pci_read_config()
206 rc = reg->u.w.read(s, reg_entry, in xen_pt_pci_read_config()
212 rc = reg->u.dw.read(s, reg_entry, in xen_pt_pci_read_config()
255 XenPTReg *reg_entry = NULL; in xen_pt_pci_write_config() local
324 reg_entry = xen_pt_find_reg(reg_grp_entry, find_addr); in xen_pt_pci_write_config()
325 if (reg_entry) { in xen_pt_pci_write_config()
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H A Dxen_pt_config_init.c83 XenPTReg *reg_entry = NULL; in xen_pt_find_reg() local
88 QLIST_FOREACH(reg_entry, &reg_grp->reg_tbl_list, entries) { in xen_pt_find_reg()
89 reg = reg_entry->reg; in xen_pt_find_reg()
94 return reg_entry; in xen_pt_find_reg()
260 XenPTReg *reg_entry = NULL; in xen_pt_status_reg_init() local
267 reg_entry = xen_pt_find_reg(reg_grp_entry, PCI_CAPABILITY_LIST); in xen_pt_status_reg_init()
268 if (reg_entry) { in xen_pt_status_reg_init()
270 if (*reg_entry->ptr.half_word) { in xen_pt_status_reg_init()
1921 XenPTReg *reg_entry; in xen_pt_config_reg_init() local
1925 reg_entry = g_new0(XenPTReg, 1); in xen_pt_config_reg_init()
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/openbmc/linux/drivers/gpu/drm/tegra/
H A Drgb.c32 struct reg_entry { struct
37 static const struct reg_entry rgb_enable[] = { argument
59 static const struct reg_entry rgb_disable[] = {
82 const struct reg_entry *table, in tegra_dc_write_regs()
/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_ras.c3221 const struct amdgpu_ras_err_status_reg_entry *reg_entry, in amdgpu_ras_inst_get_memory_id_field() argument
3227 if (!reg_entry) in amdgpu_ras_inst_get_memory_id_field()
3231 AMDGPU_RAS_REG_ENTRY_OFFSET(reg_entry->hwip, instance, in amdgpu_ras_inst_get_memory_id_field()
3232 reg_entry->seg_lo, reg_entry->reg_lo); in amdgpu_ras_inst_get_memory_id_field()
3235 if ((reg_entry->flags & AMDGPU_RAS_ERR_STATUS_VALID) && in amdgpu_ras_inst_get_memory_id_field()
3245 const struct amdgpu_ras_err_status_reg_entry *reg_entry, in amdgpu_ras_inst_get_err_cnt_field() argument
3251 if (!reg_entry) in amdgpu_ras_inst_get_err_cnt_field()
3255 AMDGPU_RAS_REG_ENTRY_OFFSET(reg_entry->hwip, instance, in amdgpu_ras_inst_get_err_cnt_field()
3256 reg_entry->seg_hi, reg_entry->reg_hi); in amdgpu_ras_inst_get_err_cnt_field()
3259 if ((reg_entry->flags & AMDGPU_RAS_ERR_INFO_VALID) && in amdgpu_ras_inst_get_err_cnt_field()
H A Damdgpu_ras.h751 const struct amdgpu_ras_err_status_reg_entry *reg_entry,
755 const struct amdgpu_ras_err_status_reg_entry *reg_entry,
H A Dgfx_v9_4_3.c3773 for (k = 0; k < gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst; k++) { in gfx_v9_4_3_inst_query_ras_err_count()
3776 gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst > 1) in gfx_v9_4_3_inst_query_ras_err_count()
3780 &(gfx_v9_4_3_ce_reg_list[i].reg_entry), in gfx_v9_4_3_inst_query_ras_err_count()
3789 &(gfx_v9_4_3_ue_reg_list[i].reg_entry), in gfx_v9_4_3_inst_query_ras_err_count()
3820 for (k = 0; k < gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst; k++) { in gfx_v9_4_3_inst_reset_ras_err_count()
3823 gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst > 1) in gfx_v9_4_3_inst_reset_ras_err_count()
3827 &(gfx_v9_4_3_ce_reg_list[i].reg_entry), in gfx_v9_4_3_inst_reset_ras_err_count()
3832 &(gfx_v9_4_3_ue_reg_list[i].reg_entry), in gfx_v9_4_3_inst_reset_ras_err_count()
H A Damdgpu_gfx.h445 struct amdgpu_ras_err_status_reg_entry reg_entry; member