Searched refs:regMP1_SMN_IH_SW_INT (Results 1 – 8 of 8) sorted by relevance
| /openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/mp/ |
| H A D | mp_13_0_2_offset.h | 385 #define regMP1_SMN_IH_SW_INT … macro
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| H A D | mp_13_0_8_offset.h | 380 #define regMP1_SMN_IH_SW_INT … macro
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| H A D | mp_13_0_4_offset.h | 378 #define regMP1_SMN_IH_SW_INT … macro
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| H A D | mp_13_0_5_offset.h | 379 #define regMP1_SMN_IH_SW_INT … macro
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| H A D | mp_13_0_0_offset.h | 377 #define regMP1_SMN_IH_SW_INT … macro
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| H A D | mp_13_0_6_offset.h | 378 #define regMP1_SMN_IH_SW_INT … macro
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| /openbmc/linux/drivers/gpu/drm/amd/pm/swsmu/smu13/ |
| H A D | smu_v13_0_6_ppt.c | 1338 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT); in smu_v13_0_6_set_irq_state()
1341 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT, val); in smu_v13_0_6_set_irq_state()
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| H A D | smu_v13_0.c | 1305 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT); in smu_v13_0_set_irq_state()
1308 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT, val); in smu_v13_0_set_irq_state()
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