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Searched refs:regDAGB0_WR_VC5_CNTL_BASE_IDX (Results 1 – 5 of 5) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/mmhub/
H A Dmmhub_3_0_2_offset.h245 #define regDAGB0_WR_VC5_CNTL_BASE_IDX … macro
H A Dmmhub_3_0_0_offset.h245 #define regDAGB0_WR_VC5_CNTL_BASE_IDX … macro
H A Dmmhub_3_0_1_offset.h273 #define regDAGB0_WR_VC5_CNTL_BASE_IDX … macro
H A Dmmhub_1_8_0_offset.h203 #define regDAGB0_WR_VC5_CNTL_BASE_IDX … macro
H A Dmmhub_1_7_offset.h199 #define regDAGB0_WR_VC5_CNTL_BASE_IDX … macro