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Searched refs:reg32 (Results 1 – 25 of 40) sorted by relevance

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/openbmc/u-boot/drivers/video/
H A Divybridge_igd.c277 u32 reg32; in gma_pm_init_pre_vbios() local
293 reg32 = gtt_read(gtt_bar, 0x42004); in gma_pm_init_pre_vbios()
294 reg32 |= (1 << 14) | (1 << 15); in gma_pm_init_pre_vbios()
295 gtt_write(gtt_bar, 0x42004, reg32); in gma_pm_init_pre_vbios()
300 reg32 = gtt_read(gtt_bar, 0x45010); in gma_pm_init_pre_vbios()
301 reg32 |= (1 << 1) | (1 << 0); in gma_pm_init_pre_vbios()
302 gtt_write(gtt_bar, 0x45010, reg32); in gma_pm_init_pre_vbios()
306 reg32 = gtt_read(gtt_bar, 0x911c); in gma_pm_init_pre_vbios()
308 if (reg32 & (1 << 13)) { in gma_pm_init_pre_vbios()
318 if (reg32 & (1 << 13)) { in gma_pm_init_pre_vbios()
[all …]
H A Dbroadwell_igd.c357 u32 reg32; in igd_setup_panel() local
360 reg32 = (plat->dp_hotplug[0] & 0x7) << 2; in igd_setup_panel()
361 reg32 |= (plat->dp_hotplug[1] & 0x7) << 10; in igd_setup_panel()
362 reg32 |= (plat->dp_hotplug[2] & 0x7) << 18; in igd_setup_panel()
363 gtt_write(priv, PCH_PORT_HOTPLUG, reg32); in igd_setup_panel()
366 reg32 = (plat->port_select & 0x3) << 30; in igd_setup_panel()
367 reg32 |= (plat->power_up_delay & 0x1fff) << 16; in igd_setup_panel()
368 reg32 |= (plat->power_backlight_on_delay & 0x1fff); in igd_setup_panel()
369 gtt_write(priv, PCH_PP_ON_DELAYS, reg32); in igd_setup_panel()
372 reg32 = (plat->power_down_delay & 0x1fff) << 16; in igd_setup_panel()
[all …]
/openbmc/u-boot/arch/x86/cpu/broadwell/
H A Dsata.c43 u32 reg32; in broadwell_sata_init() local
62 dm_pci_read_config32(dev, 0x98, &reg32); in broadwell_sata_init()
63 reg32 &= ~((1 << 31) | (1 << 30)); in broadwell_sata_init()
64 reg32 |= 1 << 23; in broadwell_sata_init()
65 reg32 |= 1 << 24; /* Enable MPHY Dynamic Power Gating */ in broadwell_sata_init()
66 dm_pci_write_config32(dev, 0x98, reg32); in broadwell_sata_init()
74 reg32 = 0x183; in broadwell_sata_init()
75 reg32 |= (plat->port_map ^ 0xf) << 24; in broadwell_sata_init()
76 reg32 |= (plat->devslp_mux & 1) << 15; in broadwell_sata_init()
77 dm_pci_write_config32(dev, 0x94, reg32); in broadwell_sata_init()
[all …]
H A Dpch.c111 u32 reg32; in pch_enable_ioapic() local
117 reg32 = io_apic_read(0x01); in pch_enable_ioapic()
120 reg32 &= ~0x00ff0000; in pch_enable_ioapic()
121 reg32 |= 0x00270000; in pch_enable_ioapic()
123 io_apic_write(0x01, reg32); in pch_enable_ioapic()
378 u32 reg32; in pch_cg_init() local
410 reg32 = readl(RCB_REG(CG)); in pch_cg_init()
412 reg32 &= ~(1 << 29); /* LPC Dynamic */ in pch_cg_init()
414 reg32 |= (1 << 29); /* LPC Dynamic */ in pch_cg_init()
415 reg32 |= 1 << 31; /* LP LPC */ in pch_cg_init()
[all …]
/openbmc/u-boot/arch/x86/cpu/ivybridge/
H A Dsata.c20 u32 reg32; in common_sata_init() local
24 reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0; in common_sata_init()
25 dm_pci_write_config32(dev, IDE_CONFIG, reg32); in common_sata_init()
44 u32 reg32; in bd82x6x_sata_init() local
77 reg32 = readl(abar + 0x00); in bd82x6x_sata_init()
78 reg32 |= 0x0c006000; /* set PSC+SSC+SALP+SSS */ in bd82x6x_sata_init()
79 reg32 &= ~0x00020060; /* clear SXS+EMS+PMS */ in bd82x6x_sata_init()
82 reg32 &= ~0x00f00000; in bd82x6x_sata_init()
83 reg32 |= (speed_support & 0x03) << 20; in bd82x6x_sata_init()
85 writel(reg32, abar + 0x00); in bd82x6x_sata_init()
[all …]
H A Dlpc.c31 u32 reg32; in pch_enable_apic() local
42 reg32 = readl(IO_APIC_DATA); in pch_enable_apic()
44 writel(reg32, IO_APIC_DATA); in pch_enable_apic()
47 reg32 = readl(IO_APIC_DATA); in pch_enable_apic()
48 debug("PCH APIC ID = %x\n", (reg32 >> 24) & 0x0f); in pch_enable_apic()
49 if (reg32 != (1 << 25)) { in pch_enable_apic()
58 reg32 = readl(IO_APIC_DATA); in pch_enable_apic()
59 debug(" 0x%08x\n", reg32); in pch_enable_apic()
133 u32 reg32; in pch_power_options() local
223 reg32 = inl(pmbase + 0x04); /* PM1_CNT */ in pch_power_options()
[all …]
/openbmc/u-boot/board/tqc/tqm834x/
H A Dpci.c56 u32 reg32; in pci_init_board() local
68 reg32 = OCCR_PCICOE1; in pci_init_board()
71 reg32 = 0xff000000; in pci_init_board()
76 reg32 |= (OCCR_PCI1CR | OCCR_PCI2CR); in pci_init_board()
78 reg32 |= (OCCR_PCICD0 | OCCR_PCICD1 | OCCR_PCICD2 \ in pci_init_board()
83 clk->occr = reg32; in pci_init_board()
/openbmc/linux/drivers/pci/pcie/
H A Daer.c146 u32 reg32; in enable_ecrc_checking() local
151 pci_read_config_dword(dev, aer + PCI_ERR_CAP, &reg32); in enable_ecrc_checking()
152 if (reg32 & PCI_ERR_CAP_ECRC_GENC) in enable_ecrc_checking()
153 reg32 |= PCI_ERR_CAP_ECRC_GENE; in enable_ecrc_checking()
154 if (reg32 & PCI_ERR_CAP_ECRC_CHKC) in enable_ecrc_checking()
155 reg32 |= PCI_ERR_CAP_ECRC_CHKE; in enable_ecrc_checking()
156 pci_write_config_dword(dev, aer + PCI_ERR_CAP, reg32); in enable_ecrc_checking()
170 u32 reg32; in disable_ecrc_checking() local
175 pci_read_config_dword(dev, aer + PCI_ERR_CAP, &reg32); in disable_ecrc_checking()
176 reg32 &= ~(PCI_ERR_CAP_ECRC_GENE | PCI_ERR_CAP_ECRC_CHKE); in disable_ecrc_checking()
[all …]
H A Daspm.c171 u32 reg32; in pcie_clkpm_cap_init() local
178 pcie_capability_read_dword(child, PCI_EXP_LNKCAP, &reg32); in pcie_clkpm_cap_init()
179 if (!(reg32 & PCI_EXP_LNKCAP_CLKPM)) { in pcie_clkpm_cap_init()
789 u32 reg32; in pcie_aspm_sanity_check() local
812 pcie_capability_read_dword(child, PCI_EXP_DEVCAP, &reg32); in pcie_aspm_sanity_check()
813 if (!(reg32 & PCI_EXP_DEVCAP_RBER) && !aspm_force) { in pcie_aspm_sanity_check()
H A Dportdrv.c78 u32 reg32; in pcie_message_numbers() local
83 &reg32); in pcie_message_numbers()
84 *aer = (reg32 & PCI_ERR_ROOT_AER_IRQ) >> 27; in pcie_message_numbers()
/openbmc/qemu/tests/qtest/
H A Dpnv-xive2-test.c217 uint32_t reg32; in test_hw_irq() local
236 reg32 = get_tima32(qts, target_pir, TM_QW3_HV_PHYS + TM_WORD0); in test_hw_irq()
237 nsr = reg32 >> 24; in test_hw_irq()
238 cppr = (reg32 >> 16) & 0xFF; in test_hw_irq()
250 reg32 = qtest_readl(qts, xive_get_queue_addr(end_index)); in test_hw_irq()
251 g_assert_cmphex((reg32 & 0x7fffffff), ==, (irq_data & 0x7fffffff)); in test_hw_irq()
260 reg32 = get_tima32(qts, target_pir, TM_QW3_HV_PHYS + TM_WORD0); in test_hw_irq()
261 nsr = reg32 >> 24; in test_hw_irq()
262 cppr = (reg32 >> 16) & 0xFF; in test_hw_irq()
/openbmc/linux/drivers/pci/
H A Dpci-acpi.c288 u32 reg32; in program_hpx_type2() local
338 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, &reg32); in program_hpx_type2()
339 reg32 = (reg32 & hpx->unc_err_mask_and) | hpx->unc_err_mask_or; in program_hpx_type2()
340 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, reg32); in program_hpx_type2()
343 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, &reg32); in program_hpx_type2()
344 reg32 = (reg32 & hpx->unc_err_sever_and) | hpx->unc_err_sever_or; in program_hpx_type2()
345 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, reg32); in program_hpx_type2()
348 pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, &reg32); in program_hpx_type2()
349 reg32 = (reg32 & hpx->cor_err_mask_and) | hpx->cor_err_mask_or; in program_hpx_type2()
350 pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg32); in program_hpx_type2()
[all …]
/openbmc/u-boot/drivers/sound/
H A Dhda_codec.c87 u32 reg32 = readl(&regs->icii); in hda_wait_for_ready() local
89 if (!(reg32 & HDA_ICII_BUSY)) in hda_wait_for_ready()
100 u32 reg32; in wait_for_response() local
107 reg32 = readl(&regs->icii); in wait_for_response()
108 if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) == in wait_for_response()
127 u32 reg32; in set_bits() local
138 reg32 = readl(port) & mask; in set_bits()
139 } while (reg32 != val && --count); in set_bits()
/openbmc/linux/drivers/infiniband/hw/hfi1/
H A Daspm.c49 u32 reg32; in aspm_hw_set_l1_ent_latency() local
51 pci_read_config_dword(dd->pcidev, PCIE_CFG_REG_PL3, &reg32); in aspm_hw_set_l1_ent_latency()
52 reg32 &= ~PCIE_CFG_REG_PL3_L1_ENT_LATENCY_SMASK; in aspm_hw_set_l1_ent_latency()
53 reg32 |= l1_ent_lat << PCIE_CFG_REG_PL3_L1_ENT_LATENCY_SHIFT; in aspm_hw_set_l1_ent_latency()
54 pci_write_config_dword(dd->pcidev, PCIE_CFG_REG_PL3, reg32); in aspm_hw_set_l1_ent_latency()
H A Dpcie.c940 u32 reg32, fs, lf; in do_pcie_gen3_transition() local
1062 reg32 = 0x10ul << PCIE_CFG_REG_PL2_LOW_PWR_ENT_CNT_SHIFT; in do_pcie_gen3_transition()
1063 pci_write_config_dword(dd->pcidev, PCIE_CFG_REG_PL2, reg32); in do_pcie_gen3_transition()
1072 reg32 = PCIE_CFG_REG_PL100_EQ_EIEOS_CNT_SMASK; in do_pcie_gen3_transition()
1073 pci_write_config_dword(dd->pcidev, PCIE_CFG_REG_PL100, reg32); in do_pcie_gen3_transition()
1331 ret = pci_read_config_dword(dd->pcidev, PCIE_CFG_SPCIE2, &reg32); in do_pcie_gen3_transition()
1338 dd_dev_info(dd, "%s: per-lane errors: 0x%x\n", __func__, reg32); in do_pcie_gen3_transition()
/openbmc/linux/drivers/net/wireless/ath/ath9k/
H A Dar9002_phy.c69 u32 freq, ndiv, channelSel = 0, channelFrac = 0, reg32 = 0; in ar9002_hw_set_channel() local
76 reg32 = REG_READ(ah, AR_PHY_SYNTH_CONTROL); in ar9002_hw_set_channel()
77 reg32 &= 0xc0000000; in ar9002_hw_set_channel()
149 reg32 = reg32 | in ar9002_hw_set_channel()
153 REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32); in ar9002_hw_set_channel()
H A Dar5008_phy.c111 static void ar5008_hw_phy_modify_rx_buffer(u32 *rfBuf, u32 reg32, in ar5008_hw_phy_modify_rx_buffer() argument
118 tmp32 = ath9k_hw_reverse_bits(reg32, numBits); in ar5008_hw_phy_modify_rx_buffer()
209 u32 reg32 = 0; in ar5008_hw_set_channel() local
264 reg32 = in ar5008_hw_set_channel()
268 REG_WRITE(ah, AR_PHY(0x37), reg32); in ar5008_hw_set_channel()
H A Dar9003_phy.c152 u32 freq, chan_frac, div, channelSel = 0, reg32 = 0; in ar9003_hw_set_channel() local
205 reg32 = (bMode << 29); in ar9003_hw_set_channel()
206 REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32); in ar9003_hw_set_channel()
213 reg32 = (channelSel << 2) | (fracMode << 30) | in ar9003_hw_set_channel()
215 REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32); in ar9003_hw_set_channel()
219 reg32 = (channelSel << 2) | (fracMode << 30) | in ar9003_hw_set_channel()
221 REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32); in ar9003_hw_set_channel()
/openbmc/linux/drivers/ipack/carriers/
H A Dtpci200.c522 u32 reg32; in tpci200_pci_probe() local
556 reg32 = ioread32(tpci200->info->cfg_regs + LAS1_DESC); in tpci200_pci_probe()
557 reg32 |= 1 << LAS_BIT_BIGENDIAN; in tpci200_pci_probe()
558 iowrite32(reg32, tpci200->info->cfg_regs + LAS1_DESC); in tpci200_pci_probe()
560 reg32 = ioread32(tpci200->info->cfg_regs + LAS2_DESC); in tpci200_pci_probe()
561 reg32 |= 1 << LAS_BIT_BIGENDIAN; in tpci200_pci_probe()
562 iowrite32(reg32, tpci200->info->cfg_regs + LAS2_DESC); in tpci200_pci_probe()
/openbmc/linux/drivers/gpu/drm/bridge/cadence/
H A Dcdns-mhdp8546-core.c879 u32 reg32; in cdns_mhdp_link_training_init() local
886 reg32 = CDNS_PHY_COMMON_CONFIG | CDNS_PHY_TRAINING_TYPE(1); in cdns_mhdp_link_training_init()
888 reg32 |= CDNS_PHY_SCRAMBLER_BYPASS; in cdns_mhdp_link_training_init()
890 cdns_mhdp_reg_write(mhdp, CDNS_DPTX_PHY_CONFIG, reg32); in cdns_mhdp_link_training_init()
1050 u32 reg32; in cdns_mhdp_link_training_channel_eq() local
1057 reg32 = CDNS_PHY_COMMON_CONFIG | CDNS_PHY_TRAINING_EN | in cdns_mhdp_link_training_channel_eq()
1060 reg32 |= CDNS_PHY_SCRAMBLER_BYPASS; in cdns_mhdp_link_training_channel_eq()
1061 cdns_mhdp_reg_write(mhdp, CDNS_DPTX_PHY_CONFIG, reg32); in cdns_mhdp_link_training_channel_eq()
1267 u32 reg32; in cdns_mhdp_link_training() local
1325 ret = cdns_mhdp_reg_read(mhdp, CDNS_DP_FRAMER_GLOBAL_CONFIG, &reg32); in cdns_mhdp_link_training()
[all …]
/openbmc/linux/drivers/gpu/drm/i915/gt/
H A Dintel_rps.h63 bool rps_read_mask_mmio(struct intel_rps *rps, i915_reg_t reg32, u32 mask);
/openbmc/linux/kernel/debug/kdb/
H A Dkdb_main.c1888 u32 reg32; in kdb_rd() local
1919 rname = dbg_get_reg(i, &reg32, kdb_current_regs); in kdb_rd()
1922 len += kdb_printf("%s: %08x", rname, reg32); in kdb_rd()
1957 u32 reg32; in kdb_rm() local
1996 reg32 = reg64; in kdb_rm()
1997 dbg_set_reg(i, &reg32, kdb_current_regs); in kdb_rm()
/openbmc/qemu/target/mips/tcg/
H A Dmips16e_translate.c.inc774 int reg32;
820 reg32 = (((ctx->opcode >> 3) & 0x3) << 3) |
822 gen_arith(ctx, OPC_ADDU, reg32, rz, 0);
826 reg32 = ctx->opcode & 0x1f;
827 gen_arith(ctx, OPC_ADDU, ry, reg32, 0);
/openbmc/linux/drivers/net/ethernet/freescale/fman/
H A Dfman_memac.c907 u32 reg32 = 0; in memac_init() local
941 reg32 = ioread32be(&memac->regs->command_config); in memac_init()
942 reg32 &= ~CMD_CFG_CRC_FWD; in memac_init()
943 iowrite32be(reg32, &memac->regs->command_config); in memac_init()
/openbmc/u-boot/drivers/serial/
H A Dserial_lpuart.c465 struct lpuart_fsl_reg32 *reg32 = plat->reg; in lpuart_serial_pending() local
472 lpuart_read32(plat->flags, &reg32->stat, &stat); in lpuart_serial_pending()

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