/openbmc/linux/arch/microblaze/kernel/ |
H A D | hw_exception_handler.S | 142 #define BSRLI2(rD, rA) \ argument 143 srl rD, rA; /* << 1 */ \ 144 srl rD, rD; /* << 2 */ 145 #define BSRLI4(rD, rA) \ argument 146 BSRLI2(rD, rA); \ 147 BSRLI2(rD, rD) 148 #define BSRLI10(rD, rA) \ argument 149 srl rD, rA; /* << 1 */ \ 150 srl rD, rD; /* << 2 */ \ 151 srl rD, rD; /* << 3 */ \ [all …]
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/openbmc/qemu/target/ppc/translate/ |
H A D | spe-impl.c.inc | 27 /* rD := rA */ 28 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); 29 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); 65 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \ 67 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \ 93 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \ 97 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \ 117 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \ 121 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \ 151 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \ [all …]
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H A D | fp-impl.c.inc | 115 set_fpr(rD(ctx->opcode), t1); \ 333 set_fpr(rD(ctx->opcode), t1); 350 set_fpr(rD(ctx->opcode), t0); 370 set_fpr(rD(ctx->opcode), t1); 390 set_fpr(rD(ctx->opcode), t1); 413 set_fpr(rD(ctx->opcode), t2); 435 set_fpr(rD(ctx->opcode), t1); 453 set_fpr(rD(ctx->opcode), t2); 751 set_fpr(rD(ctx->opcode), t0); 773 set_fpr(rD(ctx->opcode) + 1, t0); [all …]
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H A D | vmx-impl.c.inc | 118 set_avr64(rD(ctx->opcode), avr, true); 122 set_avr64(rD(ctx->opcode), avr, false); 171 set_avr64(rD(ctx->opcode), avr, false); 175 set_avr64(rD(ctx->opcode), avr, false); 182 set_avr64(rD(ctx->opcode), avr, false); 183 set_avr64(rD(ctx->opcode), z, true); 188 set_avr64(rD(ctx->opcode), avr, true); 210 avr_full_offset(rD(ctx->opcode)), \ 226 rd = gen_avr_ptr(rD(ctx->opcode)); \ 250 rd = gen_avr_ptr(rD(ctx->opcode)); \ [all …]
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H A D | vsx-impl.c.inc | 636 int xt = rD(ctx->opcode) + 32; \ 921 xt = gen_vsr_ptr(rD(ctx->opcode) + 32); \ 937 xt = gen_vsr_ptr(rD(ctx->opcode) + 32); \ 1864 TCGv rt = cpu_gpr[rD(ctx->opcode)]; 1891 set_cpu_vsr(rD(ctx->opcode) + 32, xth, true); 1893 set_cpu_vsr(rD(ctx->opcode) + 32, xtl, false); 1944 set_cpu_vsr(rD(ctx->opcode) + 32, xth, true); 1946 set_cpu_vsr(rD(ctx->opcode) + 32, xtl, false); 1951 TCGv rt = cpu_gpr[rD(ctx->opcode)]; 2001 set_cpu_vsr(rD(ctx->opcode) + 32, xth, true); [all …]
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/openbmc/linux/tools/testing/selftests/powerpc/stringloops/ |
H A D | memcmp_64.S | 17 #define rD r27 macro 271 LD rD,off8,r4 287 cmpld cr1,rC,rD 290 LD rD,off8,r4 312 cmpld cr1,rC,rD 316 LD rD,off8,r4 336 cmpld cr1,rC,rD 361 cmpld cr1,rC,rD
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/openbmc/linux/arch/powerpc/lib/ |
H A D | memcmp_64.S | 17 #define rD r27 macro 271 LD rD,off8,r4 287 cmpld cr1,rC,rD 290 LD rD,off8,r4 312 cmpld cr1,rC,rD 316 LD rD,off8,r4 336 cmpld cr1,rC,rD 361 cmpld cr1,rC,rD
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/openbmc/qemu/target/ppc/ |
H A D | translate.c | 2655 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ 2672 tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_LOAD, ldop);\ 2716 cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_STORE, stop); \ 2766 t1 = tcg_constant_i32(rD(ctx->opcode)); in gen_lmw() 2802 int start = rD(ctx->opcode); in gen_lswi() 2839 t1 = tcg_constant_i32(rD(ctx->opcode)); in gen_lswx() 2934 TCGv gpr = cpu_gpr[rD(ctx->opcode)]; in gen_load_locked() 2974 tcg_gen_movcond_tl(cond, cpu_gpr[rD(ctx->opcode)], t, t2, t, in LARX() 2982 int rt = rD(ctx->opcode); in gen_ld_atomic() 3094 src = cpu_gpr[rD(ctx->opcode)]; in gen_st_atomic() [all …]
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H A D | internal.h | 110 EXTRACT_HELPER(rD, 21, 5);
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