Home
last modified time | relevance | path

Searched refs:qla4_83xx_reg (Results 1 – 7 of 7) sorted by relevance

/openbmc/linux/drivers/scsi/qla4xxx/
H A Dql4_isr.c665 mailbox_out = &ha->qla4_83xx_reg->mailbox_out[0]; in qla4xxx_isr_decode_mailbox()
1030 readl(&ha->qla4_83xx_reg->mailbox_out[0])); in qla4_83xx_interrupt_service_routine()
1032 writel(0, &ha->qla4_83xx_reg->risc_intr); in qla4_83xx_interrupt_service_routine()
1038 writel(0, &ha->qla4_83xx_reg->mb_int_mask); in qla4_83xx_interrupt_service_routine()
1290 leg_int_ptr = readl(&ha->qla4_83xx_reg->leg_int_ptr); in qla4_83xx_intr_handler()
1313 writel(0, &ha->qla4_83xx_reg->leg_int_trig); in qla4_83xx_intr_handler()
1315 leg_int_ptr = readl(&ha->qla4_83xx_reg->leg_int_ptr); in qla4_83xx_intr_handler()
1321 leg_int_ptr = readl(&ha->qla4_83xx_reg->risc_intr); in qla4_83xx_intr_handler()
1359 ival = readl(&ha->qla4_83xx_reg->risc_intr); in qla4_83xx_mailbox_intr_handler()
1364 ival = readl(&ha->qla4_83xx_reg->mb_int_mask); in qla4_83xx_mailbox_intr_handler()
[all …]
H A Dql4_iocb.c196 writel(ha->request_in, &ha->qla4_83xx_reg->req_q_in); in qla4_83xx_queue_iocb()
197 readl(&ha->qla4_83xx_reg->req_q_in); in qla4_83xx_queue_iocb()
202 writel(ha->response_out, &ha->qla4_83xx_reg->rsp_q_out); in qla4_83xx_complete_iocb()
203 readl(&ha->qla4_83xx_reg->rsp_q_out); in qla4_83xx_complete_iocb()
H A Dql4_83xx.c1273 ret = readl(&ha->qla4_83xx_reg->mbox_int); in qla4_83xx_disable_mbox_intrs()
1275 writel(mb_int, &ha->qla4_83xx_reg->mbox_int); in qla4_83xx_disable_mbox_intrs()
1276 writel(1, &ha->qla4_83xx_reg->leg_int_mask); in qla4_83xx_disable_mbox_intrs()
1300 writel(mb_int, &ha->qla4_83xx_reg->mbox_int); in qla4_83xx_enable_mbox_intrs()
1301 writel(0, &ha->qla4_83xx_reg->leg_int_mask); in qla4_83xx_enable_mbox_intrs()
1321 writel(mbx_cmd[i], &ha->qla4_83xx_reg->mailbox_in[i]); in qla4_83xx_queue_mbox_cmd()
1323 writel(mbx_cmd[0], &ha->qla4_83xx_reg->mailbox_in[0]); in qla4_83xx_queue_mbox_cmd()
1328 writel(HINT_MBX_INT_PENDING, &ha->qla4_83xx_reg->host_intr); in qla4_83xx_queue_mbox_cmd()
1335 intr_status = readl(&ha->qla4_83xx_reg->risc_intr); in qla4_83xx_process_mbox_intr()
H A Dql4_init.c109 (unsigned long __iomem *)&ha->qla4_83xx_reg->req_q_in); in qla4xxx_init_rings()
111 (unsigned long __iomem *)&ha->qla4_83xx_reg->rsp_q_in); in qla4xxx_init_rings()
113 (unsigned long __iomem *)&ha->qla4_83xx_reg->rsp_q_out); in qla4xxx_init_rings()
H A Dql4_def.h819 struct device_reg_83xx __iomem *qla4_83xx_reg; /* Base I/O address member
H A Dql4_nx.c3601 writel(0, &ha->qla4_83xx_reg->risc_intr); in qla4_8xxx_load_risc()
3602 readl(&ha->qla4_83xx_reg->risc_intr); in qla4_8xxx_load_risc()
H A Dql4_os.c5492 writel(0, &ha->qla4_83xx_reg->risc_intr); in qla4xxx_free_adapter()
5493 readl(&ha->qla4_83xx_reg->risc_intr); in qla4xxx_free_adapter()
5567 ha->qla4_83xx_reg = (struct device_reg_83xx __iomem *) in qla4_8xxx_iospace_config()