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Searched refs:pwr_reg (Results 1 – 25 of 40) sorted by relevance

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/openbmc/linux/sound/soc/codecs/
H A Dwm8961.c197 u16 pwr_reg = snd_soc_component_read(component, WM8961_PWR_MGMT_2); in wm8961_hp_event() local
212 pwr_reg |= WM8961_LOUT1_PGA | WM8961_ROUT1_PGA; in wm8961_hp_event()
213 snd_soc_component_write(component, WM8961_PWR_MGMT_2, pwr_reg); in wm8961_hp_event()
271 pwr_reg &= ~(WM8961_LOUT1_PGA | WM8961_ROUT1_PGA); in wm8961_hp_event()
272 snd_soc_component_write(component, WM8961_PWR_MGMT_2, pwr_reg); in wm8961_hp_event()
287 u16 pwr_reg = snd_soc_component_read(component, WM8961_PWR_MGMT_2); in wm8961_spk_event() local
292 pwr_reg |= WM8961_SPKL_PGA | WM8961_SPKR_PGA; in wm8961_spk_event()
293 snd_soc_component_write(component, WM8961_PWR_MGMT_2, pwr_reg); in wm8961_spk_event()
306 pwr_reg &= ~(WM8961_SPKL_PGA | WM8961_SPKR_PGA); in wm8961_spk_event()
307 snd_soc_component_write(component, WM8961_PWR_MGMT_2, pwr_reg); in wm8961_spk_event()
H A Dwm8940.c480 u16 pwr_reg = snd_soc_component_read(component, WM8940_POWER1) & 0x1F0; in wm8940_set_bias_level() local
486 pwr_reg |= (1 << 2) | (1 << 3); in wm8940_set_bias_level()
493 ret = snd_soc_component_write(component, WM8940_POWER1, pwr_reg | 0x1); in wm8940_set_bias_level()
497 pwr_reg |= (1 << 2) | (1 << 3); in wm8940_set_bias_level()
498 ret = snd_soc_component_write(component, WM8940_POWER1, pwr_reg | 0x1); in wm8940_set_bias_level()
510 pwr_reg |= (1 << 2) | (1 << 3); in wm8940_set_bias_level()
512 ret = snd_soc_component_write(component, WM8940_POWER1, pwr_reg | 0x2); in wm8940_set_bias_level()
515 ret = snd_soc_component_write(component, WM8940_POWER1, pwr_reg); in wm8940_set_bias_level()
H A Dwm8971.c564 u16 pwr_reg = snd_soc_component_read(component, WM8971_PWR1) & 0xfe3e; in wm8971_set_bias_level() local
569 snd_soc_component_write(component, WM8971_PWR1, pwr_reg | 0x00c1); in wm8971_set_bias_level()
579 snd_soc_component_write(component, WM8971_PWR1, pwr_reg | 0x01c0); in wm8971_set_bias_level()
584 snd_soc_component_write(component, WM8971_PWR1, pwr_reg | 0x0140); in wm8971_set_bias_level()
H A Dwm8750.c624 u16 pwr_reg = snd_soc_component_read(component, WM8750_PWR1) & 0xfe3e; in wm8750_set_bias_level() local
629 snd_soc_component_write(component, WM8750_PWR1, pwr_reg | 0x00c0); in wm8750_set_bias_level()
638 snd_soc_component_write(component, WM8750_PWR1, pwr_reg | 0x01c1); in wm8750_set_bias_level()
645 snd_soc_component_write(component, WM8750_PWR1, pwr_reg | 0x0141); in wm8750_set_bias_level()
H A Dwm8988.c726 u16 pwr_reg = snd_soc_component_read(component, WM8988_PWR1) & ~0x1c1; in wm8988_set_bias_level() local
734 snd_soc_component_write(component, WM8988_PWR1, pwr_reg | 0x00c0); in wm8988_set_bias_level()
742 snd_soc_component_write(component, WM8988_PWR1, pwr_reg | 0x1c1); in wm8988_set_bias_level()
749 snd_soc_component_write(component, WM8988_PWR1, pwr_reg | 0x0141); in wm8988_set_bias_level()
H A Dwm8958-dsp2.c327 int pwr_reg = snd_soc_component_read(component, WM8994_POWER_MANAGEMENT_5); in wm8958_dsp_apply() local
332 pwr_reg &= (WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC1R_ENA); in wm8958_dsp_apply()
336 pwr_reg &= (WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA); in wm8958_dsp_apply()
340 pwr_reg &= (WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA); in wm8958_dsp_apply()
352 if (!pwr_reg) in wm8958_dsp_apply()
358 path, wm8994->dsp_active, start, pwr_reg, reg); in wm8958_dsp_apply()
H A Dwm8753.c1334 u16 pwr_reg = snd_soc_component_read(component, WM8753_PWR1) & 0xfe3e; in wm8753_set_bias_level() local
1339 snd_soc_component_write(component, WM8753_PWR1, pwr_reg | 0x00c0); in wm8753_set_bias_level()
1348 snd_soc_component_write(component, WM8753_PWR1, pwr_reg | 0x01c1); in wm8753_set_bias_level()
1353 snd_soc_component_write(component, WM8753_PWR1, pwr_reg | 0x0141); in wm8753_set_bias_level()
/openbmc/u-boot/drivers/clk/mediatek/
H A Dclk-mtk.c208 r = readl(priv->base + pll->pwr_reg) | CON0_PWR_ON; in mtk_apmixedsys_enable()
209 writel(r, priv->base + pll->pwr_reg); in mtk_apmixedsys_enable()
212 r = readl(priv->base + pll->pwr_reg) & ~CON0_ISO_EN; in mtk_apmixedsys_enable()
213 writel(r, priv->base + pll->pwr_reg); in mtk_apmixedsys_enable()
247 r = readl(priv->base + pll->pwr_reg) | CON0_ISO_EN; in mtk_apmixedsys_disable()
248 writel(r, priv->base + pll->pwr_reg); in mtk_apmixedsys_disable()
250 r = readl(priv->base + pll->pwr_reg) & ~CON0_PWR_ON; in mtk_apmixedsys_disable()
251 writel(r, priv->base + pll->pwr_reg); in mtk_apmixedsys_disable()
H A Dclk-mtk.h32 u32 pwr_reg; member
/openbmc/linux/drivers/mmc/host/
H A Dmmci_stm32_sdmmc.c393 pwr |= host->pwr_reg & (MCI_STM32_VSWITCHEN | in mmci_sdmmc_set_pwrreg()
661 mmci_write_pwrreg(host, host->pwr_reg | MCI_STM32_VSWITCHEN); in sdmmc_pre_sig_volt_vswitch()
673 host->pwr_reg & MCI_STM32_VSWITCHEN) { in sdmmc_post_sig_volt_switch()
674 mmci_write_pwrreg(host, host->pwr_reg | MCI_STM32_VSWITCH); in sdmmc_post_sig_volt_switch()
686 mmci_write_pwrreg(host, host->pwr_reg & in sdmmc_post_sig_volt_switch()
730 host->pwr_reg = readl_relaxed(host->base + MMCIPOWER); in sdmmc_variant_init()
/openbmc/linux/drivers/pinctrl/renesas/
H A Dpinctrl-rzg2l.c558 u32 pwr_reg = 0x0; in rzg2l_pinctrl_pinconf_get() local
561 pwr_reg = SD_CH(0); in rzg2l_pinctrl_pinconf_get()
563 pwr_reg = SD_CH(1); in rzg2l_pinctrl_pinconf_get()
565 pwr_reg = QSPI; in rzg2l_pinctrl_pinconf_get()
570 addr = pctrl->base + pwr_reg; in rzg2l_pinctrl_pinconf_get()
655 u32 pwr_reg = 0x0; in rzg2l_pinctrl_pinconf_set() local
661 pwr_reg = SD_CH(0); in rzg2l_pinctrl_pinconf_set()
663 pwr_reg = SD_CH(1); in rzg2l_pinctrl_pinconf_set()
665 pwr_reg = QSPI; in rzg2l_pinctrl_pinconf_set()
669 addr = pctrl->base + pwr_reg; in rzg2l_pinctrl_pinconf_set()
/openbmc/linux/drivers/clk/mediatek/
H A Dclk-mt8195-apusys_pll.c32 .pwr_reg = _pwr_reg, \
H A Dclk-mt7981-apmixed.c29 .id = _id, .name = _name, .reg = _reg, .pwr_reg = _pwr_reg, \
H A Dclk-mt8135-apmixedsys.c24 .pwr_reg = _pwr_reg, \
H A Dclk-mt7986-apmixed.c27 .id = _id, .name = _name, .reg = _reg, .pwr_reg = _pwr_reg, \
H A Dclk-pll.h30 u32 pwr_reg; member
H A Dclk-mt8516-apmixedsys.c29 .pwr_reg = _pwr_reg, \
H A Dclk-mt8167-apmixedsys.c28 .pwr_reg = _pwr_reg, \
H A Dclk-mt8188-apmixedsys.c40 .pwr_reg = _pwr_reg, \
H A Dclk-mt7622-apmixedsys.c26 .pwr_reg = _pwr_reg, \
H A Dclk-mt2712-apmixedsys.c28 .pwr_reg = _pwr_reg, \
H A Dclk-mt8365-apmixedsys.c26 .pwr_reg = _pwr_reg, \
H A Dclk-mt8186-apmixedsys.c26 .pwr_reg = _pwr_reg, \
H A Dclk-mt8183-apmixedsys.c62 .pwr_reg = _pwr_reg, \
H A Dclk-mt8173-apmixedsys.c30 .pwr_reg = _pwr_reg, \

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