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Searched refs:prefer_i64 (Results 1 – 7 of 7) sorted by relevance

/openbmc/qemu/tcg/
H A Dtcg-op-gvec.c449 uint32_t size, bool prefer_i64) in choose_vector_type() argument
478 if (TCG_TARGET_HAS_v64 && !prefer_i64 && check_size_impl(size, 8) in choose_vector_type()
1211 type = choose_vector_type(g->opt_opc, g->vece, oprsz, g->prefer_i64); in tcg_gen_gvec_2()
1275 type = choose_vector_type(g->opt_opc, g->vece, oprsz, g->prefer_i64); in tcg_gen_gvec_2i()
1341 type = choose_vector_type(g->opt_opc, g->vece, oprsz, g->prefer_i64); in tcg_gen_gvec_2s()
1421 type = choose_vector_type(g->opt_opc, g->vece, oprsz, g->prefer_i64); in tcg_gen_gvec_3()
1488 type = choose_vector_type(g->opt_opc, g->vece, oprsz, g->prefer_i64); in tcg_gen_gvec_3i()
1556 type = choose_vector_type(g->opt_opc, g->vece, oprsz, g->prefer_i64); in tcg_gen_gvec_4()
1626 type = choose_vector_type(g->opt_opc, g->vece, oprsz, g->prefer_i64); in tcg_gen_gvec_4i()
1696 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in tcg_gen_gvec_mov()
[all …]
/openbmc/qemu/include/tcg/
H A Dtcg-op-gvec-common.h99 bool prefer_i64; member
120 bool prefer_i64; member
141 bool prefer_i64; member
162 bool prefer_i64; member
183 bool prefer_i64; member
206 bool prefer_i64; member
227 bool prefer_i64; member
/openbmc/qemu/target/arm/tcg/
H A Dgengvec.c168 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in gen_gvec_ssra()
244 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in gen_gvec_usra()
352 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in gen_gvec_srshr()
442 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in gen_gvec_srsra()
546 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in gen_gvec_urshr()
655 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in gen_gvec_ursra()
739 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in gen_gvec_sri()
826 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in gen_gvec_sli()
930 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in gen_gvec_mla()
962 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in gen_gvec_mls()
[all …]
H A Dgengvec64.c160 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in gen_gvec_eor3()
186 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in gen_gvec_bcax()
H A Dtranslate-sve.c617 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in gen_bsl1n()
661 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in gen_bsl2n()
690 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in gen_nbsl()
1319 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in trans_AND_pppp()
1357 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in trans_BIC_pppp()
1388 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in trans_EOR_pppp()
1435 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in trans_ORR_pppp()
1466 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in trans_ORN_pppp()
1494 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in trans_NOR_pppp()
1522 .prefer_i64 = TCG_TARGET_REG_BITS == 64, in trans_NAND_pppp()
[all …]
/openbmc/qemu/target/riscv/insn_trans/
H A Dtrans_rvv.c.inc1361 .prefer_i64 = TCG_TARGET_REG_BITS == 64,
/openbmc/qemu/target/i386/tcg/
H A Demit.c.inc2989 .prefer_i64 = TCG_TARGET_REG_BITS == 64