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Searched refs:prcm (Results 1 – 25 of 68) sorted by relevance

123

/openbmc/u-boot/arch/arm/mach-omap2/omap5/
H A Dhw_data.c21 struct prcm_regs const **prcm = variable
386 (*prcm)->cm_l4per_clkstctrl, in enable_basic_clocks()
387 (*prcm)->cm_l3init_clkstctrl, in enable_basic_clocks()
388 (*prcm)->cm_memif_clkstctrl, in enable_basic_clocks()
389 (*prcm)->cm_l4cfg_clkstctrl, in enable_basic_clocks()
391 (*prcm)->cm_gmac_clkstctrl, in enable_basic_clocks()
397 (*prcm)->cm_l3_gpmc_clkctrl, in enable_basic_clocks()
398 (*prcm)->cm_memif_emif_1_clkctrl, in enable_basic_clocks()
399 (*prcm)->cm_memif_emif_2_clkctrl, in enable_basic_clocks()
400 (*prcm)->cm_l4cfg_l4_cfg_clkctrl, in enable_basic_clocks()
[all …]
H A Dhwinit.c219 clk_val = readl((*prcm)->cm_coreaon_io_srcomp_clkctrl); in srcomp_enable()
221 writel(clk_val, (*prcm)->cm_coreaon_io_srcomp_clkctrl); in srcomp_enable()
273 clk_val = readl((*prcm)->cm_coreaon_io_srcomp_clkctrl); in srcomp_enable()
275 writel(clk_val, (*prcm)->cm_coreaon_io_srcomp_clkctrl); in srcomp_enable()
277 clk_val = readl((*prcm)->cm_wkupaon_io_srcomp_clkctrl); in srcomp_enable()
279 writel(clk_val, (*prcm)->cm_wkupaon_io_srcomp_clkctrl); in srcomp_enable()
427 writel(PRM_RSTCTRL_RESET << 0x1, (*prcm)->prm_rstctrl); in reset_cpu()
429 writel(PRM_RSTCTRL_RESET, (*prcm)->prm_rstctrl); in reset_cpu()
434 return readl((*prcm)->prm_rstst) & PRM_RSTST_WARM_RESET_MASK; in warm_reset()
452 rst_val = readl((*prcm)->prm_rsttime) & ~RSTTIME1_MASK; in setup_warmreset_time()
[all …]
H A Ddra7xx_iodelay.c28 clrsetbits_le32((*prcm)->prm_io_pmctrl, PMCTRL_ISOCLK_OVERRIDE_MASK, in isolate_io()
31 (u32 *)(*prcm)->prm_io_pmctrl, LDELAY)) in isolate_io()
41 clrsetbits_le32((*prcm)->prm_io_pmctrl, PMCTRL_ISOCLK_OVERRIDE_MASK, in isolate_io()
45 (u32 *)(*prcm)->prm_io_pmctrl, LDELAY)) in isolate_io()
/openbmc/linux/arch/arm/mach-omap2/
H A Dclkt2xxx_virt_prcm_set.c101 const struct prcm_config *prcm; in omap2_select_table_rate() local
105 for (prcm = rate_table; prcm->mpu_speed; prcm++) { in omap2_select_table_rate()
106 if (!(prcm->flags & cpu_mask)) in omap2_select_table_rate()
109 if (prcm->xtal_speed != sys_ck_rate) in omap2_select_table_rate()
112 if (prcm->mpu_speed <= rate) { in omap2_select_table_rate()
113 found_speed = prcm->mpu_speed; in omap2_select_table_rate()
124 curr_prcm_set = prcm; in omap2_select_table_rate()
127 if (prcm->dpll_speed == cur_rate / 2) { in omap2_select_table_rate()
129 } else if (prcm->dpll_speed == cur_rate * 2) { in omap2_select_table_rate()
131 } else if (prcm->dpll_speed != cur_rate) { in omap2_select_table_rate()
[all …]
H A Domap_hwmod_2xxx_ipblock_data.c196 .prcm = {
211 .prcm = {
226 .prcm = {
241 .prcm = {
256 .prcm = {
271 .prcm = {
286 .prcm = {
301 .prcm = {
316 .prcm = {
331 .prcm = {
[all …]
H A Domap_hwmod_81xx_data.c167 .prcm = {
194 .prcm = {
236 .prcm = {
273 .prcm = {
294 .prcm = {
315 .prcm = {
353 .prcm = {
390 .prcm = {
410 .prcm = {
482 .prcm = {
[all …]
H A Domap_hwmod_3xxx_data.c104 .prcm = {
153 .prcm = {
168 .prcm = {
183 .prcm = {
198 .prcm = {
213 .prcm = {
228 .prcm = {
243 .prcm = {
258 .prcm = {
273 .prcm = {
[all …]
H A Domap_hwmod_2430_data.c75 .prcm = {
98 .prcm = {
113 .prcm = {
128 .prcm = {
141 .prcm = {
173 .prcm = {
217 .prcm = {
233 .prcm = {
249 .prcm = {
265 .prcm = {
[all …]
H A Domap_hwmod_2420_data.c96 .prcm = {
116 .prcm = {
132 .prcm = {
160 .prcm = {
176 .prcm = {
206 .prcm = {
220 .prcm = {
H A DMakefile111 omap-prcm-4-5-common = cminst44xx.o prm44xx.o \
114 obj-$(CONFIG_ARCH_OMAP4) += $(omap-prcm-4-5-common)
115 obj-$(CONFIG_SOC_OMAP5) += $(omap-prcm-4-5-common)
116 obj-$(CONFIG_SOC_DRA7XX) += $(omap-prcm-4-5-common)
117 am33xx-43xx-prcm-common += prm33xx.o cm33xx.o
118 obj-$(CONFIG_SOC_TI81XX) += $(am33xx-43xx-prcm-common)
119 obj-$(CONFIG_SOC_AM33XX) += $(am33xx-43xx-prcm-common)
120 obj-$(CONFIG_SOC_AM43XX) += $(omap-prcm-4-5-common) \
121 $(am33xx-43xx-prcm-common)
H A Domap_hwmod.c763 if (!oh->prcm.omap4.modulemode) in _omap4_xlate_clkctrl()
768 oh->prcm.omap4.clkctrl_offs); in _omap4_xlate_clkctrl()
1006 if (oh->prcm.omap4.flags & HWMOD_OMAP4_CLKFWK_CLKCTR_CLOCK) in _omap4_clkctrl_managed_by_clkfwk()
1018 if (oh->prcm.omap4.clkctrl_offs) in _omap4_has_clkctrl_clock()
1021 if (!oh->prcm.omap4.clkctrl_offs && in _omap4_has_clkctrl_clock()
1022 oh->prcm.omap4.flags & HWMOD_OMAP4_ZERO_CLKCTRL_OFFSET) in _omap4_has_clkctrl_clock()
1067 if (!oh->clkdm || !oh->prcm.omap4.modulemode || in _omap4_enable_module()
1072 oh->name, __func__, oh->prcm.omap4.modulemode); in _omap4_enable_module()
1074 omap_cm_module_enable(oh->prcm.omap4.modulemode, in _omap4_enable_module()
1076 oh->clkdm->cm_inst, oh->prcm.omap4.clkctrl_offs); in _omap4_enable_module()
[all …]
/openbmc/u-boot/arch/arm/mach-omap2/omap4/
H A Dhw_data.c19 struct prcm_regs const **prcm = variable
331 (*prcm)->cm_l4per_clkstctrl, in enable_basic_clocks()
332 (*prcm)->cm_l3init_clkstctrl, in enable_basic_clocks()
333 (*prcm)->cm_memif_clkstctrl, in enable_basic_clocks()
334 (*prcm)->cm_l4cfg_clkstctrl, in enable_basic_clocks()
339 (*prcm)->cm_l3_gpmc_clkctrl, in enable_basic_clocks()
340 (*prcm)->cm_memif_emif_1_clkctrl, in enable_basic_clocks()
341 (*prcm)->cm_memif_emif_2_clkctrl, in enable_basic_clocks()
342 (*prcm)->cm_l4cfg_l4_cfg_clkctrl, in enable_basic_clocks()
343 (*prcm)->cm_wkup_gpio1_clkctrl, in enable_basic_clocks()
[all …]
H A DMakefile10 obj-y += prcm-regs.o
/openbmc/u-boot/arch/arm/mach-omap2/
H A Dclocks-common.c58 ind = (readl((*prcm)->cm_sys_clksel) & in __get_sys_clk_index()
327 (struct dpll_regs *)((*prcm)->cm_clkmode_dpll_mpu); in configure_mpu_dpll()
328 bypass_dpll((*prcm)->cm_clkmode_dpll_mpu); in configure_mpu_dpll()
329 clrbits_le32((*prcm)->cm_mpu_mpu_clkctrl, in configure_mpu_dpll()
331 setbits_le32((*prcm)->cm_mpu_mpu_clkctrl, in configure_mpu_dpll()
339 do_setup_dpll((*prcm)->cm_clkmode_dpll_mpu, params, DPLL_LOCK, "mpu"); in configure_mpu_dpll()
364 clrsetbits_le32((*prcm)->cm_clksel_dpll_usb, in setup_usb_dpll()
369 do_setup_dpll((*prcm)->cm_clkmode_dpll_usb, params, DPLL_LOCK, "usb"); in setup_usb_dpll()
390 do_setup_dpll((*prcm)->cm_clkmode_dpll_core, params, in setup_dplls()
393 do_setup_dpll((*prcm)->cm_clkmode_dpll_core, params, in setup_dplls()
[all …]
H A Dvc.c77 writel(val, (*prcm)->prm_vc_cfg_i2c_clk); in omap_vc_init()
85 writel(val, (*prcm)->prm_vc_cfg_i2c_mode); in omap_vc_init()
111 writel(reg_val, (*prcm)->prm_vc_val_bypass); in omap_vc_bypass_send_value()
115 (*prcm)->prm_vc_val_bypass); in omap_vc_bypass_send_value()
119 reg_val = readl((*prcm)->prm_vc_val_bypass) & in omap_vc_bypass_send_value()
/openbmc/u-boot/arch/arm/mach-sunxi/
H A Dprcm.c26 struct sunxi_prcm_reg *prcm = in prcm_apb0_enable() local
30 setbits_le32(&prcm->apb0_gate, flags); in prcm_apb0_enable()
33 setbits_le32(&prcm->apb0_reset, flags); in prcm_apb0_enable()
38 struct sunxi_prcm_reg *prcm = in prcm_apb0_disable() local
42 clrbits_le32(&prcm->apb0_reset, flags); in prcm_apb0_disable()
45 clrbits_le32(&prcm->apb0_gate, flags); in prcm_apb0_disable()
H A Dclock_sun6i.c25 struct sunxi_prcm_reg * const prcm = in clock_init_safe() local
29 clrsetbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK, in clock_init_safe()
31 clrsetbits_le32(&prcm->pll_ctrl1, ~PRCM_PLL_CTRL_LDO_KEY_MASK, in clock_init_safe()
34 clrbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK); in clock_init_safe()
68 struct sunxi_prcm_reg * const prcm = in clock_init_sec() local
75 setbits_le32(&prcm->prcm_sec_switch, in clock_init_sec()
/openbmc/u-boot/arch/arm/mach-omap2/omap3/
H A Dclock.c30 struct prcm *prcm_base = (struct prcm *)PRCM_BASE; in get_osc_clk_speed()
121 struct prcm *prcm_base = (struct prcm *)PRCM_BASE; in dpll3_init_34xx()
233 struct prcm *prcm_base = (struct prcm *)PRCM_BASE; in dpll4_init_34xx()
286 struct prcm *prcm_base = (struct prcm *)PRCM_BASE; in dpll5_init_34xx()
310 struct prcm *prcm_base = (struct prcm *)PRCM_BASE; in mpu_init_34xx()
337 struct prcm *prcm_base = (struct prcm *)PRCM_BASE; in iva_init_34xx()
378 struct prcm *prcm_base = (struct prcm *)PRCM_BASE; in dpll3_init_36xx()
483 struct prcm *prcm_base = (struct prcm *)PRCM_BASE; in dpll4_init_36xx()
526 struct prcm *prcm_base = (struct prcm *)PRCM_BASE; in dpll5_init_36xx()
548 struct prcm *prcm_base = (struct prcm *)PRCM_BASE; in mpu_init_36xx()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/arm/omap/
H A Dprcm.txt12 "ti,am3-prcm"
13 "ti,am4-prcm"
14 "ti,omap2-prcm"
28 "ti,dm814-prcm"
29 "ti,dm816-prcm"
/openbmc/u-boot/board/ti/omap5_uevm/
H A Devm.c165 setbits_le32((*prcm)->cm_l3init_hsusbhost_clkctrl, hs_clk_ctrl_val); in enable_host_clocks()
168 setbits_le32((*prcm)->cm_l3init_hsusbtll_clkctrl, in enable_host_clocks()
172 setbits_le32((*prcm)->cm_l3init_usb_otg_ss_clkctrl, in enable_host_clocks()
176 auxclk = readl((*prcm)->scrm_auxclk1); in enable_host_clocks()
179 writel(auxclk, (*prcm)->scrm_auxclk1); in enable_host_clocks()
/openbmc/u-boot/board/compulab/cm_t54/
H A Dcm_t54.c207 setbits_le32((*prcm)->cm_l3init_hsusbhost_clkctrl, usbhost_clk); in setup_host_clocks()
209 setbits_le32((*prcm)->cm_l3init_hsusbtll_clkctrl, usbtll_clk); in setup_host_clocks()
214 clrbits_le32((*prcm)->cm_l3init_hsusbtll_clkctrl, usbtll_clk); in setup_host_clocks()
215 clrbits_le32((*prcm)->cm_l3init_hsusbhost_clkctrl, usbhost_clk); in setup_host_clocks()
/openbmc/u-boot/board/htkw/mcx/
H A Dmcx.c126 struct prcm *prcm_base = (struct prcm *)PRCM_BASE; in board_video_init()
/openbmc/u-boot/arch/arm/cpu/armv7/sunxi/
H A Dpsci.c160 struct sunxi_prcm_reg *prcm = in sunxi_cpu_set_power() local
163 sunxi_power_switch(&prcm->cpu_pwr_clamp[cpu], &prcm->cpu_pwroff, in sunxi_cpu_set_power()
/openbmc/u-boot/board/compulab/common/
H A Domap3_display.c398 struct prcm *prcm = (struct prcm *)PRCM_BASE; in lcd_ctrl_init() local
421 clrsetbits_le32(&prcm->clksel_dss, 0xF, 3); in lcd_ctrl_init()
/openbmc/linux/arch/arm/boot/dts/ti/omap/
H A Domap2420.dtsi20 prcm: prcm@8000 { label
21 compatible = "ti,omap2-prcm";

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