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Searched refs:ppll_div_3 (Results 1 – 6 of 6) sorted by relevance

/openbmc/u-boot/drivers/video/
H A Dati_radeon_fb.c215 (mode->ppll_div_3 == (INPLL(PPLL_DIV_3) & in radeon_write_pll_regs()
264 OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_FB3_DIV_MASK); in radeon_write_pll_regs()
265 OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_POST3_DIV_MASK); in radeon_write_pll_regs()
343 mode->ppll_div_3 = 0x00030059; in radeon_setmode()
396 mode->ppll_div_3 = 0x00010078; in radeon_setmode_9200()
399 mode->ppll_div_3 = 0x00010060; in radeon_setmode_9200()
427 mode->ppll_div_3 = 0x0002008c; in radeon_setmode_9200()
433 mode->ppll_div_3 = 0x00020074; in radeon_setmode_9200()
458 mode->ppll_div_3 = 0x000300b0; in radeon_setmode_9200()
463 mode->ppll_div_3 = 0x0003008e; in radeon_setmode_9200()
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H A Dati_radeon_fb.h227 u32 ppll_div_3; member
/openbmc/linux/drivers/video/fbdev/aty/
H A Dradeon_base.c1342 save->ppll_div_3 = INPLL(PPLL_DIV_3); in radeon_save_state()
1363 (mode->ppll_div_3 == (INPLL(PPLL_DIV_3) & in radeon_write_pll_regs()
1412 OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_FB3_DIV_MASK); in radeon_write_pll_regs()
1413 OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_POST3_DIV_MASK); in radeon_write_pll_regs()
1631 regs->ppll_div_3 = fb_div | (post_div->bitvalue << 16); in radeon_calc_pll_regs()
1635 pr_debug("ppll_div_3 = 0x%x\n", regs->ppll_div_3); in radeon_calc_pll_regs()
1699 newmode->ppll_div_3 = rinfo->panel_info.fbk_divider | in radeonfb_set_par()
H A Dradeonfb.h236 u32 ppll_div_3; member
/openbmc/linux/drivers/gpu/drm/radeon/
H A Dradeon_legacy_tv.c874 uint32_t *ppll_div_3, uint32_t *pixclks_cntl) in radeon_legacy_tv_adjust_pll1() argument
887 *ppll_div_3 = (const_ptr->crtcPLL_N & 0x7ff) | (get_post_div(const_ptr->crtcPLL_post_div) << 16); in radeon_legacy_tv_adjust_pll1()
H A Dradeon_mode.h927 uint32_t *ppll_div_3, uint32_t *pixclks_cntl);