Searched refs:pp_offset (Results 1 – 6 of 6) sorted by relevance
66 u8 pp_offset; member127 u64 pp_offset :8; member328 pd_info->sst_header.pp_offset + in sst_add_perf_profiles()331 perf_level_offsets = readq(pd_info->sst_base + pd_info->sst_header.pp_offset + in sst_add_perf_profiles()341 pd_info->perf_levels[i].mmio_offset = pd_info->sst_header.pp_offset + offset; in sst_add_perf_profiles()353 pd_info->sst_header.pp_offset *= 8; in sst_main()365 *((u64 *)&pd_info->pp_header) = readq(pd_info->sst_base + pd_info->sst_header.pp_offset); in sst_main()630 val = readq(power_domain_info->sst_base + power_domain_info->sst_header.pp_offset +\642 val = readq(power_domain_info->sst_base + power_domain_info->sst_header.pp_offset +\647 writeq(val, power_domain_info->sst_base + power_domain_info->sst_header.pp_offset +\[all …]
190 static const u32 pp_offset[PINGPONG_MAX] = {0xC, 0x8, 0x4, 0x13, 0x18}; in dpu_hw_setup_vsync_source_and_vsync_sel() local201 if (pp_idx >= ARRAY_SIZE(pp_offset)) in dpu_hw_setup_vsync_source_and_vsync_sel()204 reg &= ~(0xf << pp_offset[pp_idx]); in dpu_hw_setup_vsync_source_and_vsync_sel()205 reg |= (cfg->vsync_source & 0xf) << pp_offset[pp_idx]; in dpu_hw_setup_vsync_source_and_vsync_sel()
215 return scnprintf(buf, PAGE_SIZE, "%llu\n", afu->native->pp_offset); in pp_mmio_off_show()
854 afu->native->pp_offset = AFUD_READ_PPPSA_OFF(afu); in cxl_read_afu_descriptor()885 (afu->native->pp_offset + afu->pp_size*afu->max_procs_virtualised)) { in cxl_afu_descriptor_looks_ok()
463 u64 pp_offset; member
543 (ctx->afu->native->pp_offset + ctx->afu->pp_size * ctx->pe); in cxl_assign_psn_space()