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Searched refs:pllcfgr (Results 1 – 5 of 5) sorted by relevance

/openbmc/u-boot/drivers/clk/
H A Dclk_stm32f.c156 writel(0x24003010, &regs->pllcfgr); /* Reset value from RM */ in configure_clocks()
171 setbits_le32(&regs->pllcfgr, RCC_PLLCFGR_PLLSRC); /* pll source HSE */ in configure_clocks()
172 clrsetbits_le32(&regs->pllcfgr, RCC_PLLCFGR_PLLM_MASK, in configure_clocks()
174 clrsetbits_le32(&regs->pllcfgr, RCC_PLLCFGR_PLLN_MASK, in configure_clocks()
176 clrsetbits_le32(&regs->pllcfgr, RCC_PLLCFGR_PLLP_MASK, in configure_clocks()
178 clrsetbits_le32(&regs->pllcfgr, RCC_PLLCFGR_PLLQ_MASK, in configure_clocks()
280 pllm = (readl(&regs->pllcfgr) & RCC_PLLCFGR_PLLM_MASK); in stm32_clk_get_pllsai_vco_rate()
405 pllm = (readl(&regs->pllcfgr) & RCC_PLLCFGR_PLLM_MASK); in stm32_clk_get_rate()
406 plln = ((readl(&regs->pllcfgr) & RCC_PLLCFGR_PLLN_MASK) in stm32_clk_get_rate()
408 pllp = ((((readl(&regs->pllcfgr) & RCC_PLLCFGR_PLLP_MASK) in stm32_clk_get_rate()
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H A Dclk_stm32h7.c131 u32 pllcfgr; /* 0x2c PLLs Configuration Register */ member
352 uint32_t pllcfgr = 0; in configure_clocks() local
403 pllcfgr |= PLL1RGE_4_8_MHZ << RCC_PLLCFGR_PLL1RGE_SHIFT; in configure_clocks()
404 pllcfgr |= RCC_PLLCFGR_DIVP1EN; in configure_clocks()
405 pllcfgr |= RCC_PLLCFGR_DIVQ1EN; in configure_clocks()
406 pllcfgr |= RCC_PLLCFGR_DIVR1EN; in configure_clocks()
407 writel(pllcfgr, &regs->pllcfgr); in configure_clocks()
/openbmc/u-boot/include/
H A Dstm32_rcc.h61 u32 pllcfgr; /* RCC PLL configuration */ member
/openbmc/qemu/hw/misc/
H A Dstm32l4x5_rcc.c746 reg = s->pllcfgr; in rcc_update_pllsaixcfgr()
811 val = FIELD_EX32(s->pllcfgr, PLLCFGR, PLLM); in rcc_update_pllcfgr()
815 val = FIELD_EX32(s->pllcfgr, PLLCFGR, PLLSRC); in rcc_update_pllcfgr()
933 s->pllcfgr = 0x00001000; in stm32l4x5_rcc_reset_hold()
978 retvalue = s->pllcfgr; in stm32l4x5_rcc_read()
1095 s->pllcfgr = value; in stm32l4x5_rcc_write()
1348 VMSTATE_UINT32(pllcfgr, Stm32l4x5RccState),
/openbmc/qemu/include/hw/misc/
H A Dstm32l4x5_rcc.h190 uint32_t pllcfgr; member