Searched refs:pllc1 (Results 1 – 3 of 3) sorted by relevance
75 writel(cfg->main_pll_pllc1, &clock_manager_base->main_pll.pllc1); in cm_basic_init()97 writel(cfg->per_pll_pllc1, &clock_manager_base->per_pll.pllc1); in cm_basic_init()281 clock /= (readl(&clock_manager_base->main_pll.pllc1) & in cm_get_l3_main_clk_hz()287 clock /= (readl(&clock_manager_base->per_pll.pllc1) & in cm_get_l3_main_clk_hz()
95 u32 pllc1; member122 u32 pllc1; member
484 clock-output-names = "system", "pllc0", "pllc1",