Home
last modified time | relevance | path

Searched refs:pll_settings (Results 1 – 11 of 11) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_clock_source.c193 struct pll_settings *pll_settings, in calc_fb_divider_checking_tolerance() argument
206 pll_settings->adjusted_pix_clk_100hz, in calc_fb_divider_checking_tolerance()
225 pll_settings->adjusted_pix_clk_100hz) in calc_fb_divider_checking_tolerance()
227 pll_settings->adjusted_pix_clk_100hz in calc_fb_divider_checking_tolerance()
228 : pll_settings->adjusted_pix_clk_100hz - in calc_fb_divider_checking_tolerance()
233 pll_settings->reference_freq = calc_pll_cs->ref_freq_khz; in calc_fb_divider_checking_tolerance()
234 pll_settings->reference_divider = ref_divider; in calc_fb_divider_checking_tolerance()
235 pll_settings->feedback_divider = feedback_divider; in calc_fb_divider_checking_tolerance()
236 pll_settings->fract_feedback_divider = fract_feedback_divider; in calc_fb_divider_checking_tolerance()
237 pll_settings->pix_clk_post_divider = post_divider; in calc_fb_divider_checking_tolerance()
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/inc/
H A Dclock_source.h106 struct pll_settings { struct
167 struct pll_settings *);
171 struct pll_settings *);
H A Dcore_types.h376 struct pll_settings pll_settings; member
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn314/
H A Ddcn314_hwseq.c462 &pipe_ctx->pll_settings); in apply_symclk_on_tx_off_wa()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dce110/
H A Ddce110_hw_sequencer.c1360 pipe_ctx->pll_settings.feedback_divider; in build_audio_output()
1370 pipe_ctx->pll_settings.ss_percentage; in build_audio_output()
1441 &pipe_ctx->pll_settings)) { in dce110_enable_stream_timing()
3084 &pipes[i].pll_settings); in dce110_enable_dp_link_output()
H A Ddce110_resource.c923 &pipe_ctx->pll_settings); in dce110_resource_build_pipe_hw_param()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_resource.c1044 &pipe_ctx->pll_settings); in build_pipe_hw_param()
H A Ddcn10_hw_sequencer.c928 &pipe_ctx->pll_settings)) { in dcn10_enable_stream_timing()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn32/
H A Ddcn32_hwseq.c1313 &pipe_ctx->pll_settings); in apply_symclk_on_tx_off_wa()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_resource.c1283 &pipe_ctx->pll_settings); in build_pipe_hw_param()
H A Ddcn20_hwseq.c728 &pipe_ctx->pll_settings)) { in dcn20_enable_stream_timing()