Home
last modified time | relevance | path

Searched refs:pll_div (Results 1 – 25 of 44) sorted by relevance

12

/openbmc/linux/drivers/clk/x86/
H A Dclk-lgm.c124 static const struct clk_div_table pll_div[] = { variable
196 0, PLL_DIV_WIDTH, 24, 1, 0, 0, pll_div),
198 4, PLL_DIV_WIDTH, 25, 1, 0, 0, pll_div),
200 8, PLL_DIV_WIDTH, 26, 1, 0, 0, pll_div),
202 12, PLL_DIV_WIDTH, 27, 1, 0, 0, pll_div),
205 pll_div),
207 0, PLL_DIV_WIDTH, 24, 1, 0, 0, pll_div),
211 1, 0, 0, pll_div),
214 8, PLL_DIV_WIDTH, 26, 1, 0, 0, pll_div),
218 0, PLL_DIV_WIDTH, 24, 1, 0, 0, pll_div),
[all …]
/openbmc/linux/sound/soc/codecs/
H A Dwm8804.c319 struct pll_div { struct
344 static int pll_factors(struct pll_div *pll_div, unsigned int target, in pll_factors() argument
359 pll_div->freqmode = post_table[i].freqmode; in pll_factors()
360 pll_div->mclkdiv = post_table[i].mclkdiv; in pll_factors()
372 pll_div->prescale = 0; in pll_factors()
376 pll_div->prescale = 1; in pll_factors()
385 pll_div->n = Ndiv; in pll_factors()
396 pll_div->k = K; in pll_factors()
417 struct pll_div pll_div; in wm8804_set_pll() local
419 ret = pll_factors(&pll_div, freq_out, freq_in, in wm8804_set_pll()
[all …]
H A Dwm8580.c400 static int pll_factors(struct _pll_div *pll_div, unsigned int target, in pll_factors() argument
415 pll_div->freqmode = post_table[i].freqmode; in pll_factors()
416 pll_div->postscale = post_table[i].postscale; in pll_factors()
432 pll_div->prescale = 1; in pll_factors()
435 pll_div->prescale = 0; in pll_factors()
443 pll_div->n = Ndiv; in pll_factors()
451 pll_div->k = K; in pll_factors()
454 pll_div->n, pll_div->k, pll_div->prescale, pll_div->freqmode, in pll_factors()
455 pll_div->postscale); in pll_factors()
467 struct _pll_div pll_div; in wm8580_set_dai_pll() local
[all …]
H A Dwm9713.c753 struct _pll_div *pll_div, unsigned int source) in pll_factors() argument
764 pll_div->divsel = 1; in pll_factors()
768 pll_div->divctl = 1; in pll_factors()
770 pll_div->divctl = 0; in pll_factors()
773 pll_div->divsel = 0; in pll_factors()
774 pll_div->divctl = 0; in pll_factors()
781 pll_div->lf = 1; in pll_factors()
784 pll_div->lf = 0; in pll_factors()
792 pll_div->n = Ndiv; in pll_factors()
807 pll_div->k = K; in pll_factors()
[all …]
H A Dwm8940.c528 static struct pll_ pll_div; variable
543 pll_div.pre_scale = 0; in pll_factors()
548 pll_div.pre_scale = 3; in pll_factors()
553 pll_div.pre_scale = 2; in pll_factors()
556 pll_div.pre_scale = 1; in pll_factors()
563 pll_div.n = Ndiv; in pll_factors()
578 pll_div.k = K; in pll_factors()
603 if (pll_div.k) in wm8940_set_dai_pll()
605 (pll_div.pre_scale << 4) | pll_div.n | (1 << 6)); in wm8940_set_dai_pll()
608 (pll_div.pre_scale << 4) | pll_div.n); in wm8940_set_dai_pll()
[all …]
H A Dwm8978.c409 struct wm8978_pll_div *pll_div, unsigned int target, unsigned int source) in pll_factors() argument
417 pll_div->div2 = 1; in pll_factors()
420 pll_div->div2 = 0; in pll_factors()
428 pll_div->n = n_div; in pll_factors()
436 pll_div->k = k; in pll_factors()
474 struct wm8978_pll_div pll_div; in wm8978_configure_pll() local
536 pll_factors(component, &pll_div, f2, wm8978->f_mclk); in wm8978_configure_pll()
539 __func__, pll_div.n, pll_div.k, pll_div.div2); in wm8978_configure_pll()
544 snd_soc_component_write(component, WM8978_PLL_N, (pll_div.div2 << 4) | pll_div.n); in wm8978_configure_pll()
545 snd_soc_component_write(component, WM8978_PLL_K1, pll_div.k >> 18); in wm8978_configure_pll()
[all …]
H A Dwm8974.c272 static void pll_factors(struct pll_ *pll_div, in pll_factors() argument
284 pll_div->pre_div = 1; in pll_factors()
287 pll_div->pre_div = 0; in pll_factors()
294 pll_div->n = Ndiv; in pll_factors()
309 pll_div->k = K; in pll_factors()
316 struct pll_ pll_div; in wm8974_set_dai_pll() local
330 pll_factors(&pll_div, freq_out, freq_in); in wm8974_set_dai_pll()
332 snd_soc_component_write(component, WM8974_PLLN, (pll_div.pre_div << 4) | pll_div.n); in wm8974_set_dai_pll()
333 snd_soc_component_write(component, WM8974_PLLK1, pll_div.k >> 18); in wm8974_set_dai_pll()
334 snd_soc_component_write(component, WM8974_PLLK2, (pll_div.k >> 9) & 0x1ff); in wm8974_set_dai_pll()
[all …]
H A Dwm8510.c271 static struct pll_ pll_div; variable
285 pll_div.pre_div = 1; in pll_factors()
288 pll_div.pre_div = 0; in pll_factors()
295 pll_div.n = Ndiv; in pll_factors()
310 pll_div.k = K; in pll_factors()
332 snd_soc_component_write(component, WM8510_PLLN, (pll_div.pre_div << 4) | pll_div.n); in wm8510_set_dai_pll()
333 snd_soc_component_write(component, WM8510_PLLK1, pll_div.k >> 18); in wm8510_set_dai_pll()
334 snd_soc_component_write(component, WM8510_PLLK2, (pll_div.k >> 9) & 0x1ff); in wm8510_set_dai_pll()
335 snd_soc_component_write(component, WM8510_PLLK3, pll_div.k & 0x1ff); in wm8510_set_dai_pll()
H A Dwm8983.c743 struct pll_div { struct
750 static int pll_factors(struct pll_div *pll_div, unsigned int target, in pll_factors() argument
756 pll_div->div2 = 0; in pll_factors()
760 pll_div->div2 = 1; in pll_factors()
769 pll_div->n = Ndiv; in pll_factors()
780 pll_div->k = K; in pll_factors()
790 struct pll_div pll_div; in wm8983_set_pll() local
799 ret = pll_factors(&pll_div, freq_out * 4 * 2, freq_in); in wm8983_set_pll()
809 (pll_div.div2 << WM8983_PLL_PRESCALE_SHIFT) in wm8983_set_pll()
810 | pll_div.n); in wm8983_set_pll()
[all …]
H A Dwm8985.c840 struct pll_div { struct
847 static int pll_factors(struct pll_div *pll_div, unsigned int target, in pll_factors() argument
853 pll_div->div2 = 0; in pll_factors()
857 pll_div->div2 = 1; in pll_factors()
866 pll_div->n = Ndiv; in pll_factors()
877 pll_div->k = K; in pll_factors()
888 struct pll_div pll_div; in wm8985_set_pll() local
896 ret = pll_factors(&pll_div, freq_out * 4 * 2, freq_in); in wm8985_set_pll()
902 (pll_div.div2 << WM8985_PLL_PRESCALE_SHIFT) in wm8985_set_pll()
903 | pll_div.n); in wm8985_set_pll()
[all …]
H A Dwm8960.c1164 struct _pll_div *pll_div) in pll_factors() argument
1177 pll_div->pre_div = 1; in pll_factors()
1180 pll_div->pre_div = 0; in pll_factors()
1187 pll_div->n = Ndiv; in pll_factors()
1202 pll_div->k = K; in pll_factors()
1205 pll_div->n, pll_div->k, pll_div->pre_div); in pll_factors()
1214 static struct _pll_div pll_div; in wm8960_set_pll() local
1218 ret = pll_factors(freq_in, freq_out, &pll_div); in wm8960_set_pll()
1232 reg |= pll_div.pre_div << 4; in wm8960_set_pll()
1233 reg |= pll_div.n; in wm8960_set_pll()
[all …]
H A Dwm8990.c806 static void pll_factors(struct _pll_div *pll_div, unsigned int target, in pll_factors() argument
816 pll_div->div2 = 1; in pll_factors()
819 pll_div->div2 = 0; in pll_factors()
825 pll_div->n = Ndiv; in pll_factors()
840 pll_div->k = K; in pll_factors()
847 struct _pll_div pll_div; in wm8990_set_dai_pll() local
850 pll_factors(&pll_div, freq_out * 4, freq_in); in wm8990_set_dai_pll()
861 snd_soc_component_write(component, WM8990_PLL1, pll_div.n | WM8990_SDM | in wm8990_set_dai_pll()
862 (pll_div.div2?WM8990_PRESCALE:0)); in wm8990_set_dai_pll()
863 snd_soc_component_write(component, WM8990_PLL2, (u8)(pll_div.k>>8)); in wm8990_set_dai_pll()
[all …]
H A Dwm8991.c877 static void pll_factors(struct _pll_div *pll_div, unsigned int target, in pll_factors() argument
887 pll_div->div2 = 1; in pll_factors()
890 pll_div->div2 = 0; in pll_factors()
896 pll_div->n = Ndiv; in pll_factors()
911 pll_div->k = K; in pll_factors()
919 struct _pll_div pll_div; in wm8991_set_dai_pll() local
922 pll_factors(&pll_div, freq_out * 4, freq_in); in wm8991_set_dai_pll()
934 snd_soc_component_write(component, WM8991_PLL1, pll_div.n | WM8991_SDM | in wm8991_set_dai_pll()
935 (pll_div.div2 ? WM8991_PRESCALE : 0)); in wm8991_set_dai_pll()
936 snd_soc_component_write(component, WM8991_PLL2, (u8)(pll_div.k>>8)); in wm8991_set_dai_pll()
[all …]
H A Dwm8753.c702 static void pll_factors(struct _pll_div *pll_div, unsigned int target, in pll_factors() argument
711 pll_div->div2 = 1; in pll_factors()
714 pll_div->div2 = 0; in pll_factors()
720 pll_div->n = Ndiv; in pll_factors()
735 pll_div->k = K; in pll_factors()
765 struct _pll_div pll_div; in wm8753_set_dai_pll() local
767 pll_factors(&pll_div, freq_out * 8, freq_in); in wm8753_set_dai_pll()
771 value = (pll_div.n << 5) + ((pll_div.k & 0x3c0000) >> 18); in wm8753_set_dai_pll()
775 value = (pll_div.k & 0x03fe00) >> 9; in wm8753_set_dai_pll()
779 value = pll_div.k & 0x0001ff; in wm8753_set_dai_pll()
[all …]
/openbmc/u-boot/arch/arm/mach-davinci/
H A Dcpu.c115 static unsigned pll_div(volatile void *pllbase, unsigned offset) in pll_div() function
130 return pll_div(pllbase, PLLC_PREDIV); in pll_prediv()
132 return pll_div(pllbase, PLLC_PREDIV); in pll_prediv()
140 return pll_div(pllbase, PLLC_POSTDIV); in pll_postdiv()
143 return pll_div(pllbase, PLLC_POSTDIV); in pll_postdiv()
167 return DIV_ROUND_UP(base, 1000 * pll_div(pllbase, div)); in pll_sysclk_mhz()
/openbmc/linux/drivers/clk/imx/
H A Dclk-fracn-gppll.c155 u32 pll_numerator, pll_denominator, pll_div; in clk_fracn_gppll_recalc_rate() local
167 pll_div = readl_relaxed(pll->base + PLL_DIV); in clk_fracn_gppll_recalc_rate()
168 mfi = FIELD_GET(PLL_MFI_MASK, pll_div); in clk_fracn_gppll_recalc_rate()
170 rdiv = FIELD_GET(PLL_RDIV_MASK, pll_div); in clk_fracn_gppll_recalc_rate()
171 odiv = FIELD_GET(PLL_ODIV_MASK, pll_div); in clk_fracn_gppll_recalc_rate()
229 u32 tmp, pll_div, ana_mfn; in clk_fracn_gppll_set_rate() local
252 pll_div = FIELD_PREP(PLL_RDIV_MASK, rate->rdiv) | rate->odiv | in clk_fracn_gppll_set_rate()
254 writel_relaxed(pll_div, pll->base + PLL_DIV); in clk_fracn_gppll_set_rate()
/openbmc/linux/drivers/gpu/drm/i915/display/
H A Dvlv_dsi_pll.c123 u32 pll_ctl, pll_div; in vlv_dsi_pclk() local
129 pll_div = config->dsi_pll.div; in vlv_dsi_pclk()
136 n = (pll_div & DSI_PLL_N1_DIV_MASK) >> DSI_PLL_N1_DIV_SHIFT; in vlv_dsi_pclk()
140 pll_div &= DSI_PLL_M1_DIV_MASK; in vlv_dsi_pclk()
141 pll_div = pll_div >> DSI_PLL_M1_DIV_SHIFT; in vlv_dsi_pclk()
155 if (lfsr_converts[i] == pll_div) in vlv_dsi_pclk()
324 u32 pll_ctl, pll_div; in vlv_dsi_get_pclk() local
330 pll_div = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_DIVIDER); in vlv_dsi_get_pclk()
334 config->dsi_pll.div = pll_div; in vlv_dsi_get_pclk()
/openbmc/linux/drivers/clk/meson/
H A Dvid-pll-div.c79 struct meson_vid_pll_div_data *pll_div = meson_vid_pll_div_data(clk); in meson_vid_pll_div_recalc_rate() local
82 div = _get_table_val(meson_parm_read(clk->map, &pll_div->val), in meson_vid_pll_div_recalc_rate()
83 meson_parm_read(clk->map, &pll_div->sel)); in meson_vid_pll_div_recalc_rate()
/openbmc/u-boot/drivers/clk/rockchip/
H A Dclk_rk3399.c32 struct pll_div { struct
50 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1); argument
51 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2, 2);
53 static const struct pll_div ppll_init_cfg = PLL_DIVISORS(PPLL_HZ, 2, 2, 1);
56 static const struct pll_div apll_l_1600_cfg = PLL_DIVISORS(1600*MHz, 3, 1, 1);
57 static const struct pll_div apll_l_600_cfg = PLL_DIVISORS(600*MHz, 1, 2, 1);
59 static const struct pll_div *apll_l_cfgs[] = {
64 static const struct pll_div apll_b_600_cfg = PLL_DIVISORS(600*MHz, 1, 2, 1);
65 static const struct pll_div *apll_b_cfgs[] = {
314 static void rkclk_set_pll(u32 *pll_con, const struct pll_div *div) in rkclk_set_pll()
[all …]
H A Dclk_rk3368.c29 struct pll_div { struct
50 static const struct pll_div apll_l_init_cfg = PLL_DIVISORS(APLL_L_HZ, 12, 2); argument
51 static const struct pll_div apll_b_init_cfg = PLL_DIVISORS(APLL_B_HZ, 1, 2);
53 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 1, 2);
54 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 6);
89 const struct pll_div *div) in rkclk_set_pll()
284 const struct pll_div *dpll_cfg = NULL; in rk3368_ddr_set_clk()
288 static const struct pll_div dpll_1200 = PLL_DIVISORS(1200 * MHz, 1, 1); in rk3368_ddr_set_clk()
289 static const struct pll_div dpll_1332 = PLL_DIVISORS(1332 * MHz, 2, 1); in rk3368_ddr_set_clk()
290 static const struct pll_div dpll_1600 = PLL_DIVISORS(1600 * MHz, 3, 2); in rk3368_ddr_set_clk()
H A Dclk_rk322x.c38 static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1);
39 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
42 const struct pll_div *div) in rkclk_set_pll()
319 struct pll_div dpll_cfg; in rk322x_ddr_set_clk()
324 dpll_cfg = (struct pll_div) in rk322x_ddr_set_clk()
328 dpll_cfg = (struct pll_div) in rk322x_ddr_set_clk()
332 dpll_cfg = (struct pll_div) in rk322x_ddr_set_clk()
H A Dclk_rk3328.c20 struct pll_div { struct
37 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 1, 4, 1); argument
38 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 2, 2, 1);
40 static const struct pll_div apll_816_cfg = PLL_DIVISORS(816 * MHz, 1, 2, 1);
41 static const struct pll_div apll_600_cfg = PLL_DIVISORS(600 * MHz, 1, 3, 1);
43 static const struct pll_div *apll_cfgs[] = {
207 const struct pll_div *div) in rkclk_set_pll()
H A Dclk_rk3188.c36 struct pll_div { struct
81 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2);
82 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2);
86 const struct pll_div *div, bool has_bwadj) in rkclk_set_pll()
122 static const struct pll_div dpll_cfg[] = { in rkclk_configure_ddr()
168 static const struct pll_div apll_cfg[] = { in rkclk_configure_cpu()
/openbmc/u-boot/arch/arm/mach-imx/mx7/
H A Dclock.c775 static int enable_pll_video(u32 pll_div, u32 pll_num, u32 pll_denom, in enable_pll_video() argument
782 pll_div, pll_num, pll_denom); in enable_pll_video()
796 writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) | in enable_pll_video()
802 writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) | in enable_pll_video()
808 writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) | in enable_pll_video()
814 writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) | in enable_pll_video()
821 writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) | in enable_pll_video()
898 u32 pll_div, pll_num, pll_denom, post_div = 0; in mxs_set_lcdclk() local
942 pll_div = best / hck; in mxs_set_lcdclk()
944 pll_num = (best - hck * pll_div) * pll_denom / hck; in mxs_set_lcdclk()
[all …]
/openbmc/linux/drivers/clk/
H A Dclk-stm32f4.c720 struct stm32f4_pll_div *pll_div = to_pll_div_clk(div); in stm32f4_pll_div_set_rate() local
722 pll_state = stm32f4_pll_is_enabled(pll_div->hw_pll); in stm32f4_pll_div_set_rate()
725 stm32f4_pll_disable(pll_div->hw_pll); in stm32f4_pll_div_set_rate()
730 stm32f4_pll_enable(pll_div->hw_pll); in stm32f4_pll_div_set_rate()
747 struct stm32f4_pll_div *pll_div; in clk_register_pll_div() local
753 pll_div = kzalloc(sizeof(*pll_div), GFP_KERNEL); in clk_register_pll_div()
754 if (!pll_div) in clk_register_pll_div()
764 pll_div->div.reg = reg; in clk_register_pll_div()
765 pll_div->div.shift = shift; in clk_register_pll_div()
766 pll_div->div.width = width; in clk_register_pll_div()
[all …]

12