Searched refs:pll1_div (Results 1 – 7 of 7) sorted by relevance
26 static unsigned int pll1_div; variable43 unsigned long rate = clk->parent->rate / pll1_div; in pll_recalc()139 pll1_div = 3; in arch_clk_init()141 pll1_div = 4; in arch_clk_init()143 pll1_div = 1; in arch_clk_init()
41 u8 pll1_div; member
221 rate /= pll_config->pll1_div; in gen3_clk_get_rate64()225 pll_config->pll1_div, rate); in gen3_clk_get_rate64()
56 u8 pll1_div; member
73 u8 pll1_div; member
352 div = cpg_pll_config->pll1_div; in rcar_gen4_cpg_clk_register()
377 div = cpg_pll_config->pll1_div; in rcar_gen3_cpg_clk_register()