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Searched refs:pll10_cfg (Results 1 – 4 of 4) sorted by relevance

/openbmc/u-boot/arch/arm/mach-sunxi/
H A Dclock_sun6i.c265 clrbits_le32(&ccm->pll10_cfg, CCM_PLL10_CTRL_EN); in clock_set_pll10()
272 &ccm->pll10_cfg); in clock_set_pll10()
274 while (!(readl(&ccm->pll10_cfg) & CCM_PLL10_CTRL_LOCK)) in clock_set_pll10()
/openbmc/u-boot/arch/arm/include/asm/arch-sunxi/
H A Dclock_sun8i_a83t.h33 u32 pll10_cfg; /* 0x4c pll10 video1 control */ member
H A Dclock_sun50i_h6.h29 u32 pll10_cfg; /* 0x060 pll10 (de) control */ member
H A Dclock_sun6i.h32 u32 pll10_cfg; /* 0x48 pll10 control */ member