| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| H A D | display_rq_dlg_calc_32.c | 47 const unsigned int pipe_idx) in dml32_rq_dlg_get_rq_reg() argument
49 const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src; in dml32_rq_dlg_get_rq_reg()
74 …dml_print("DML_DLG::%s: Calculation for pipe[%d] start, num_pipes=%d\n", __func__, pipe_idx, num_p… in dml32_rq_dlg_get_rq_reg()
85 …dpte_group_bytes = get_dpte_group_size_in_bytes(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); //… in dml32_rq_dlg_get_rq_reg()
86 …mpte_group_bytes = get_vm_group_size_in_bytes(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // F… in dml32_rq_dlg_get_rq_reg()
129 …f_size_in_bytes = get_det_buffer_size_kbytes(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * 1024; in dml32_rq_dlg_get_rq_reg()
132 pipe_idx); in dml32_rq_dlg_get_rq_reg()
141 num_pipes, pipe_idx); in dml32_rq_dlg_get_rq_reg()
149 …_regs_l.swath_height = dml_log2(get_swath_height_l(mode_lib, e2e_pipe_param, num_pipes, pipe_idx)); in dml32_rq_dlg_get_rq_reg()
150 …_regs_c.swath_height = dml_log2(get_swath_height_c(mode_lib, e2e_pipe_param, num_pipes, pipe_idx)); in dml32_rq_dlg_get_rq_reg()
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| H A D | dcn32_fpu.c | 325 uint32_t i, pipe_idx; in dcn32_helper_populate_phantom_dlg_params() local
329 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { in dcn32_helper_populate_phantom_dlg_params()
336 pipes[pipe_idx].pipe.dest.vstartup_start = in dcn32_helper_populate_phantom_dlg_params()
337 get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); in dcn32_helper_populate_phantom_dlg_params()
338 pipes[pipe_idx].pipe.dest.vupdate_offset = in dcn32_helper_populate_phantom_dlg_params()
339 get_vupdate_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); in dcn32_helper_populate_phantom_dlg_params()
340 pipes[pipe_idx].pipe.dest.vupdate_width = in dcn32_helper_populate_phantom_dlg_params()
341 get_vupdate_width(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); in dcn32_helper_populate_phantom_dlg_params()
342 pipes[pipe_idx].pipe.dest.vready_offset = in dcn32_helper_populate_phantom_dlg_params()
343 get_vready_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx); in dcn32_helper_populate_phantom_dlg_params()
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| H A D | display_rq_dlg_calc_32.h | 48 const unsigned int pipe_idx);
68 const unsigned int pipe_idx);
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| H A D | display_rq_dlg_calc_31.c | 856 const unsigned int pipe_idx, in dml_rq_dlg_get_dlg_params() argument
867 const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src; in dml_rq_dlg_get_dlg_params()
868 const display_pipe_dest_params_st *dst = &e2e_pipe_param[pipe_idx].pipe.dest; in dml_rq_dlg_get_dlg_params()
869 const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg; in dml_rq_dlg_get_dlg_params()
870 const scaler_ratio_depth_st *scl = &e2e_pipe_param[pipe_idx].pipe.scale_ratio_depth; in dml_rq_dlg_get_dlg_params()
871 const scaler_taps_st *taps = &e2e_pipe_param[pipe_idx].pipe.scale_taps; in dml_rq_dlg_get_dlg_params()
958 …y_next_start = get_min_dst_y_next_start(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // FROM VBA in dml_rq_dlg_get_dlg_params()
959 …_vcount0 = get_vready_at_or_after_vsync(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA in dml_rq_dlg_get_dlg_params()
961 …fcyc_per_line_delivery_pre_l_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in… in dml_rq_dlg_get_dlg_params()
962 …t_refcyc_per_line_delivery_l_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in… in dml_rq_dlg_get_dlg_params()
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| H A D | dcn31_fpu.c | 488 int i, pipe_idx, total_det = 0, active_hubp_count = 0; in dcn31_calculate_wm_and_dlg_fp() local
529 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { in dcn31_calculate_wm_and_dlg_fp()
536 …pipes[pipe_idx].clks_cfg.dispclk_mhz = get_dispclk_calculated(&context->bw_ctx.dml, pipes, pipe_cn… in dcn31_calculate_wm_and_dlg_fp()
537 …pipes[pipe_idx].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt,… in dcn31_calculate_wm_and_dlg_fp()
540 pipes[pipe_idx].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz; in dcn31_calculate_wm_and_dlg_fp()
541 pipes[pipe_idx].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz; in dcn31_calculate_wm_and_dlg_fp()
543 if (dc->debug.min_disp_clk_khz > pipes[pipe_idx].clks_cfg.dispclk_mhz * 1000) in dcn31_calculate_wm_and_dlg_fp()
544 pipes[pipe_idx].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0; in dcn31_calculate_wm_and_dlg_fp()
545 if (dc->debug.min_dpp_clk_khz > pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000) in dcn31_calculate_wm_and_dlg_fp()
546 pipes[pipe_idx].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0; in dcn31_calculate_wm_and_dlg_fp()
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| H A D | display_rq_dlg_calc_31.h | 62 const unsigned int pipe_idx,
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dml/dcn314/ |
| H A D | display_rq_dlg_calc_314.c | 941 const unsigned int pipe_idx, in dml_rq_dlg_get_dlg_params() argument
952 const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src; in dml_rq_dlg_get_dlg_params()
953 const display_pipe_dest_params_st *dst = &e2e_pipe_param[pipe_idx].pipe.dest; in dml_rq_dlg_get_dlg_params()
954 const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg; in dml_rq_dlg_get_dlg_params()
955 const scaler_ratio_depth_st *scl = &e2e_pipe_param[pipe_idx].pipe.scale_ratio_depth; in dml_rq_dlg_get_dlg_params()
956 const scaler_taps_st *taps = &e2e_pipe_param[pipe_idx].pipe.scale_taps; in dml_rq_dlg_get_dlg_params()
1043 …y_next_start = get_min_dst_y_next_start(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // FROM VBA in dml_rq_dlg_get_dlg_params()
1044 …_vcount0 = get_vready_at_or_after_vsync(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); // From VBA in dml_rq_dlg_get_dlg_params()
1046 …fcyc_per_line_delivery_pre_l_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in… in dml_rq_dlg_get_dlg_params()
1047 …t_refcyc_per_line_delivery_l_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in… in dml_rq_dlg_get_dlg_params()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn20/ |
| H A D | dcn20_resource.c | 1312 int pipe_idx) in dcn20_acquire_dsc() argument
1316 …struct display_stream_compressor *dsc_old = dc->current_state->res_ctx.pipe_ctx[pipe_idx].stream_r… in dcn20_acquire_dsc()
1323 *dsc = pool->dscs[pipe_idx]; in dcn20_acquire_dsc()
1324 res_ctx->is_dsc_acquired[pipe_idx] = true; in dcn20_acquire_dsc()
1468 int pipe_idx = next_odm_pipe->pipe_idx; in dcn20_split_stream_for_odm() local
1473 next_odm_pipe->pipe_idx = pipe_idx; in dcn20_split_stream_for_odm()
1474 next_odm_pipe->plane_res.mi = pool->mis[next_odm_pipe->pipe_idx]; in dcn20_split_stream_for_odm()
1475 next_odm_pipe->plane_res.hubp = pool->hubps[next_odm_pipe->pipe_idx]; in dcn20_split_stream_for_odm()
1476 next_odm_pipe->plane_res.ipp = pool->ipps[next_odm_pipe->pipe_idx]; in dcn20_split_stream_for_odm()
1477 next_odm_pipe->plane_res.xfm = pool->transforms[next_odm_pipe->pipe_idx]; in dcn20_split_stream_for_odm()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dml/dcn301/ |
| H A D | dcn301_fpu.c | 418 int i, pipe_idx; in dcn301_calculate_wm_and_dlg_fp() local
453 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { in dcn301_calculate_wm_and_dlg_fp()
457 …pipes[pipe_idx].clks_cfg.dispclk_mhz = get_dispclk_calculated(&context->bw_ctx.dml, pipes, pipe_cn… in dcn301_calculate_wm_and_dlg_fp()
458 …pipes[pipe_idx].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt,… in dcn301_calculate_wm_and_dlg_fp()
461 pipes[pipe_idx].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz; in dcn301_calculate_wm_and_dlg_fp()
462 pipes[pipe_idx].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz; in dcn301_calculate_wm_and_dlg_fp()
464 if (dc->debug.min_disp_clk_khz > pipes[pipe_idx].clks_cfg.dispclk_mhz * 1000) in dcn301_calculate_wm_and_dlg_fp()
465 pipes[pipe_idx].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0; in dcn301_calculate_wm_and_dlg_fp()
466 if (dc->debug.min_dpp_clk_khz > pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000) in dcn301_calculate_wm_and_dlg_fp()
467 pipes[pipe_idx].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0; in dcn301_calculate_wm_and_dlg_fp()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| H A D | display_rq_dlg_calc_30.c | 893 const unsigned int pipe_idx, in dml_rq_dlg_get_dlg_params() argument
904 const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src; in dml_rq_dlg_get_dlg_params()
905 const display_pipe_dest_params_st *dst = &e2e_pipe_param[pipe_idx].pipe.dest; in dml_rq_dlg_get_dlg_params()
906 const display_output_params_st *dout = &e2e_pipe_param[pipe_idx].dout; in dml_rq_dlg_get_dlg_params()
907 const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg; in dml_rq_dlg_get_dlg_params()
908 const scaler_ratio_depth_st *scl = &e2e_pipe_param[pipe_idx].pipe.scale_ratio_depth; in dml_rq_dlg_get_dlg_params()
909 const scaler_taps_st *taps = &e2e_pipe_param[pipe_idx].pipe.scale_taps; in dml_rq_dlg_get_dlg_params()
1051 min_ttu_vblank = get_min_ttu_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); in dml_rq_dlg_get_dlg_params()
1126 double dsc_delay = get_dsc_delay(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); in dml_rq_dlg_get_dlg_params()
1172 dst_x_after_scaler = get_dst_x_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); in dml_rq_dlg_get_dlg_params()
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| H A D | dcn30_fpu.c | 386 int i, pipe_idx; in dcn30_fpu_calculate_wm_and_dlg() local
549 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { in dcn30_fpu_calculate_wm_and_dlg()
553 …pipes[pipe_idx].clks_cfg.dispclk_mhz = get_dispclk_calculated(&context->bw_ctx.dml, pipes, pipe_cn… in dcn30_fpu_calculate_wm_and_dlg()
554 …pipes[pipe_idx].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt,… in dcn30_fpu_calculate_wm_and_dlg()
557 pipes[pipe_idx].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz; in dcn30_fpu_calculate_wm_and_dlg()
558 pipes[pipe_idx].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz; in dcn30_fpu_calculate_wm_and_dlg()
560 if (dc->debug.min_disp_clk_khz > pipes[pipe_idx].clks_cfg.dispclk_mhz * 1000) in dcn30_fpu_calculate_wm_and_dlg()
561 pipes[pipe_idx].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0; in dcn30_fpu_calculate_wm_and_dlg()
562 if (dc->debug.min_dpp_clk_khz > pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000) in dcn30_fpu_calculate_wm_and_dlg()
563 pipes[pipe_idx].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0; in dcn30_fpu_calculate_wm_and_dlg()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dml/dcn21/ |
| H A D | display_rq_dlg_calc_21.c | 833 const unsigned int pipe_idx, in dml_rq_dlg_get_dlg_params() argument
841 const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src; in dml_rq_dlg_get_dlg_params()
842 const display_pipe_dest_params_st *dst = &e2e_pipe_param[pipe_idx].pipe.dest; in dml_rq_dlg_get_dlg_params()
843 const display_output_params_st *dout = &e2e_pipe_param[pipe_idx].dout; in dml_rq_dlg_get_dlg_params()
844 const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg; in dml_rq_dlg_get_dlg_params()
845 const scaler_ratio_depth_st *scl = &e2e_pipe_param[pipe_idx].pipe.scale_ratio_depth; in dml_rq_dlg_get_dlg_params()
846 const scaler_taps_st *taps = &e2e_pipe_param[pipe_idx].pipe.scale_taps; in dml_rq_dlg_get_dlg_params()
986 min_ttu_vblank = get_min_ttu_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); in dml_rq_dlg_get_dlg_params()
1068 double dsc_delay = get_dsc_delay(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); in dml_rq_dlg_get_dlg_params()
1117 dst_x_after_scaler = get_dst_x_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); in dml_rq_dlg_get_dlg_params()
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| H A D | display_rq_dlg_calc_21.h | 66 const unsigned int pipe_idx,
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| H A D | display_rq_dlg_calc_20.c | 49 const unsigned int pipe_idx,
787 const unsigned int pipe_idx, in dml20_rq_dlg_get_dlg_params() argument
795 const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src; in dml20_rq_dlg_get_dlg_params()
796 const display_pipe_dest_params_st *dst = &e2e_pipe_param[pipe_idx].pipe.dest; in dml20_rq_dlg_get_dlg_params()
797 const display_output_params_st *dout = &e2e_pipe_param[pipe_idx].dout; in dml20_rq_dlg_get_dlg_params()
798 const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg; in dml20_rq_dlg_get_dlg_params()
799 const scaler_ratio_depth_st *scl = &e2e_pipe_param[pipe_idx].pipe.scale_ratio_depth; in dml20_rq_dlg_get_dlg_params()
800 const scaler_taps_st *taps = &e2e_pipe_param[pipe_idx].pipe.scale_taps; in dml20_rq_dlg_get_dlg_params()
940 min_ttu_vblank = get_min_ttu_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); in dml20_rq_dlg_get_dlg_params()
1028 double dsc_delay = get_dsc_delay(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); in dml20_rq_dlg_get_dlg_params()
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| H A D | display_rq_dlg_calc_20v2.c | 49 const unsigned int pipe_idx,
787 const unsigned int pipe_idx, in dml20v2_rq_dlg_get_dlg_params() argument
795 const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src; in dml20v2_rq_dlg_get_dlg_params()
796 const display_pipe_dest_params_st *dst = &e2e_pipe_param[pipe_idx].pipe.dest; in dml20v2_rq_dlg_get_dlg_params()
797 const display_output_params_st *dout = &e2e_pipe_param[pipe_idx].dout; in dml20v2_rq_dlg_get_dlg_params()
798 const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg; in dml20v2_rq_dlg_get_dlg_params()
799 const scaler_ratio_depth_st *scl = &e2e_pipe_param[pipe_idx].pipe.scale_ratio_depth; in dml20v2_rq_dlg_get_dlg_params()
800 const scaler_taps_st *taps = &e2e_pipe_param[pipe_idx].pipe.scale_taps; in dml20v2_rq_dlg_get_dlg_params()
940 min_ttu_vblank = get_min_ttu_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); in dml20v2_rq_dlg_get_dlg_params()
1029 double dsc_delay = get_dsc_delay(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); in dml20v2_rq_dlg_get_dlg_params()
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| H A D | dcn20_fpu.c | 1140 int i, pipe_idx, active_hubp_count = 0; in dcn20_calculate_dlg_params() local
1173 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { in dcn20_calculate_dlg_params()
1178 …pipes[pipe_idx].pipe.dest.vstartup_start = get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt, pip… in dcn20_calculate_dlg_params()
1179 …pipes[pipe_idx].pipe.dest.vupdate_offset = get_vupdate_offset(&context->bw_ctx.dml, pipes, pipe_cn… in dcn20_calculate_dlg_params()
1180 …pipes[pipe_idx].pipe.dest.vupdate_width = get_vupdate_width(&context->bw_ctx.dml, pipes, pipe_cnt,… in dcn20_calculate_dlg_params()
1181 …pipes[pipe_idx].pipe.dest.vready_offset = get_vready_offset(&context->bw_ctx.dml, pipes, pipe_cnt,… in dcn20_calculate_dlg_params()
1189 context->res_ctx.pipe_ctx[i].unbounded_req = pipes[pipe_idx].pipe.src.unbounded_req_mode; in dcn20_calculate_dlg_params()
1192 if (context->bw_ctx.bw.dcn.clk.dppclk_khz < pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000) in dcn20_calculate_dlg_params()
1193 context->bw_ctx.bw.dcn.clk.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000; in dcn20_calculate_dlg_params()
1195 pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000; in dcn20_calculate_dlg_params()
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| H A D | display_rq_dlg_calc_20.h | 66 const unsigned int pipe_idx,
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dml/ |
| H A D | display_mode_lib.h | 57 const unsigned int pipe_idx,
75 const unsigned int pipe_idx);
80 const unsigned int pipe_idx);
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| H A D | display_mode_vba.c | 258 int pipe_idx = -1; in get_pipe_idx() local
265 pipe_idx = i; in get_pipe_idx()
269 ASSERT(pipe_idx >= 0); in get_pipe_idx()
271 return pipe_idx; in get_pipe_idx()
276 unsigned int num_pipes, unsigned int pipe_idx) in get_det_buffer_size_kbytes() argument
282 plane_idx = mode_lib->vba.pipe_plane[pipe_idx]; in get_det_buffer_size_kbytes()
284 …dml_print("DML::%s: num_pipes=%d pipe_idx=%d plane_idx=%0d\n", __func__, num_pipes, pipe_idx, plan… in get_det_buffer_size_kbytes()
293 unsigned int num_pipes, unsigned int pipe_idx) in get_is_phantom_pipe() argument
298 plane_idx = mode_lib->vba.pipe_plane[pipe_idx]; in get_is_phantom_pipe()
299 …nt("DML::%s: num_pipes=%d pipe_idx=%d UseMALLForPStateChange=%0d\n", __func__, num_pipes, pipe_idx, in get_is_phantom_pipe()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dce60/ |
| H A D | dce60_hw_sequencer.c | 52 uint32_t *pipe_idx) in dce60_should_enable_fbc() argument
79 if (pipe_ctx->pipe_idx != underlay_idx) { in dce60_should_enable_fbc()
80 *pipe_idx = i; in dce60_should_enable_fbc()
118 uint32_t pipe_idx = 0; in dce60_enable_fbc() local
120 if (dce60_should_enable_fbc(dc, context, &pipe_idx)) { in dce60_enable_fbc()
124 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx]; in dce60_enable_fbc()
349 pipe_ctx->pipe_idx, in dce60_program_front_end_for_pipe()
370 pipe_ctx->pipe_idx, in dce60_program_front_end_for_pipe()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/ |
| H A D | dc_dmub_srv.c | 305 int pipe_idx = 0; in dc_dmub_srv_populate_fams_pipe_info() local
307 fams_pipe_data->pipe_index[pipe_idx++] = head_pipe->plane_res.hubp->inst; in dc_dmub_srv_populate_fams_pipe_info()
312 fams_pipe_data->pipe_index[pipe_idx++] = split_pipe->plane_res.hubp->inst; in dc_dmub_srv_populate_fams_pipe_info()
315 fams_pipe_data->pipe_count = pipe_idx; in dc_dmub_srv_populate_fams_pipe_info()
325 int pipe_idx = 0; in dc_dmub_srv_p_state_delegate() local
339 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { in dc_dmub_srv_p_state_delegate()
353 pipe_idx++; in dc_dmub_srv_p_state_delegate()
550 pipe_data->pipe_config.vblank_data.vblank_pipe_index = vblank_pipe->pipe_idx; in populate_subvp_cmd_vblank_pipe_info()
677 pipe_data->pipe_config.subvp_data.main_split_pipe_index = subvp_pipe->bottom_pipe->pipe_idx; in populate_subvp_cmd_pipe_info()
679 pipe_data->pipe_config.subvp_data.main_split_pipe_index = subvp_pipe->next_odm_pipe->pipe_idx; in populate_subvp_cmd_pipe_info()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn30/ |
| H A D | dcn30_resource.c | 1528 int pipe_idx = sec_pipe->pipe_idx; in dcn30_split_stream_for_mpc_or_odm() local
1533 sec_pipe->pipe_idx = pipe_idx; in dcn30_split_stream_for_mpc_or_odm()
1534 sec_pipe->plane_res.mi = pool->mis[pipe_idx]; in dcn30_split_stream_for_mpc_or_odm()
1535 sec_pipe->plane_res.hubp = pool->hubps[pipe_idx]; in dcn30_split_stream_for_mpc_or_odm()
1536 sec_pipe->plane_res.ipp = pool->ipps[pipe_idx]; in dcn30_split_stream_for_mpc_or_odm()
1537 sec_pipe->plane_res.xfm = pool->transforms[pipe_idx]; in dcn30_split_stream_for_mpc_or_odm()
1538 sec_pipe->plane_res.dpp = pool->dpps[pipe_idx]; in dcn30_split_stream_for_mpc_or_odm()
1539 sec_pipe->plane_res.mpcc_inst = pool->dpps[pipe_idx]->inst; in dcn30_split_stream_for_mpc_or_odm()
1559 sec_pipe->stream_res.opp = pool->opps[pipe_idx]; in dcn30_split_stream_for_mpc_or_odm()
1563 dcn20_acquire_dsc(dc, res_ctx, &sec_pipe->stream_res.dsc, pipe_idx); in dcn30_split_stream_for_mpc_or_odm()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/core/ |
| H A D | dc_resource.c | 1512 pipe_ctx->pipe_idx, in resource_build_scaling_params()
1596 int preferred_pipe_idx = (pool->pipe_count - 1) - primary_pipe->pipe_idx; in resource_find_free_secondary_pipe_legacy()
1599 secondary_pipe->pipe_idx = preferred_pipe_idx; in resource_find_free_secondary_pipe_legacy()
1611 secondary_pipe->pipe_idx = i; in resource_find_free_secondary_pipe_legacy()
1633 new_pipe = &new_res_ctx->pipe_ctx[cur_sec_dpp->pipe_idx]; in resource_find_free_pipe_used_in_cur_mpc_blending_tree()
1635 free_pipe_idx = cur_sec_dpp->pipe_idx; in resource_find_free_pipe_used_in_cur_mpc_blending_tree()
1823 split_pipe->pipe_idx = i; in acquire_first_split_pipe()
1890 int pipe_idx = acquire_first_split_pipe( in acquire_secondary_dpp_pipes_and_add_plane()
1894 if (pipe_idx >= 0) in acquire_secondary_dpp_pipes_and_add_plane()
1895 sec_pipe = &new_ctx->res_ctx.pipe_ctx[pipe_idx]; in acquire_secondary_dpp_pipes_and_add_plane()
1889 int pipe_idx = acquire_first_split_pipe( acquire_secondary_dpp_pipes_and_add_plane() local
2728 int pipe_idx = -1; resource_map_pool_resources() local
4156 reset_sync_context_for_pipe(const struct dc * dc,struct dc_state * context,uint8_t pipe_idx) reset_sync_context_for_pipe() argument
4267 int pipe_idx = sec_pipe->pipe_idx; dc_resource_acquire_secondary_pipe_for_mpc_odm() local
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn21/ |
| H A D | dcn21_resource.c | 804 int pipe_cnt, i, pipe_idx, vlevel; in dcn21_fast_validate_bw() local
848 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { in dcn21_fast_validate_bw()
857 if (vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled in dcn21_fast_validate_bw()
865 pipe_idx++; in dcn21_fast_validate_bw()
872 for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) { in dcn21_fast_validate_bw()
879 pipe_idx++; in dcn21_fast_validate_bw()
881 …if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) { in dcn21_fast_validate_bw()
888 pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx; in dcn21_fast_validate_bw()
905 …djust_dppclk(&context->bw_ctx.dml.vba, vlevel, context->bw_ctx.dml.vba.maxMpcComb, pipe_idx, true); in dcn21_fast_validate_bw()
909 if (context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) { in dcn21_fast_validate_bw()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn32/ |
| H A D | dcn32_resource.c | 2547 cur_opp_head = &cur_res_ctx->pipe_ctx[new_opp_head->pipe_idx]; in find_optimal_free_pipe_as_secondary_dpp_pipe()
2606 primary_index = primary_pipe->pipe_idx; in find_idle_secondary_pipe_check_mpo()
2612 preferred_pipe_idx = (pool->pipe_count - 1) - primary_pipe->pipe_idx; in find_idle_secondary_pipe_check_mpo()
2614 !(next_odm_mpo_pipe && next_odm_mpo_pipe->pipe_idx == preferred_pipe_idx)) { in find_idle_secondary_pipe_check_mpo()
2616 secondary_pipe->pipe_idx = preferred_pipe_idx; in find_idle_secondary_pipe_check_mpo()
2627 !(next_odm_mpo_pipe && next_odm_mpo_pipe->pipe_idx == i)) { in find_idle_secondary_pipe_check_mpo()
2629 secondary_pipe->pipe_idx = i; in find_idle_secondary_pipe_check_mpo()
2657 head_index = head_pipe->pipe_idx; in dcn32_acquire_idle_pipe_for_head_pipe_in_layer()
2659 if (pipe->bottom_pipe && res_ctx->pipe_ctx[pipe->bottom_pipe->pipe_idx].stream == NULL) { in dcn32_acquire_idle_pipe_for_head_pipe_in_layer()
2660 idle_pipe = &res_ctx->pipe_ctx[pipe->bottom_pipe->pipe_idx]; in dcn32_acquire_idle_pipe_for_head_pipe_in_layer()
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