Searched refs:picsr (Results 1 – 4 of 4) sorted by relevance
117 cpu->env.picsr = 0x00000000; in openrisc_cpu_reset_hold()137 cpu->env.picsr |= irq_bit; in openrisc_cpu_set_irq()139 cpu->env.picsr &= ~irq_bit; in openrisc_cpu_set_irq()142 if (cpu->env.picsr & cpu->env.picmr) { in openrisc_cpu_set_irq()
164 if (env->picsr & env->picmr) { in HELPER()172 env->picsr &= ~rb; in HELPER()344 return env->picsr; in HELPER()
117 VMSTATE_UINT32(picsr, CPUOpenRISCState),
284 uint32_t picsr; /* Interrupt control register */ member