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Searched refs:phy_reg1_val (Results 1 – 3 of 3) sorted by relevance

/openbmc/u-boot/drivers/ddr/marvell/a38x/
H A Dddr3_init.h99 extern u32 phy_reg1_val;
H A Dddr3_training.c16 u32 phy_reg1_val = 8; variable
1903 CTX_PHY_REG(effective_cs), phy_reg1_val)); in ddr3_tip_ddr3_reset_phy_regs()
2143 ddr3_tip_adll_regs_bypass(dev_num, phy_reg1_val, 0); in ddr3_tip_ddr3_training_main_flow()
H A Dddr3_training_leveling.c966 (((reg_data & 0x1f) + phy_reg1_val) << 10); in ddr3_tip_dynamic_write_leveling()
1066 phy_reg1_val) << 10); in ddr3_tip_dynamic_write_leveling()