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Searched refs:phy1_dq (Results 1 – 3 of 3) sorted by relevance

/openbmc/u-boot/arch/arm/mach-exynos/
H A Dclock_init.h92 unsigned phy1_dq; member
H A Dclock_init_exynos5.c195 .phy1_dq = 0x08080808,
298 .phy1_dq = 0x08080808,
401 .phy1_dq = 0x08080808,
H A Ddmc_init_ddr3.c84 writel(mem->phy1_dq, &phy1_ctrl->phy_con6); in ddr3_mem_ctrl_init()