Searched refs:phy0_ctrl (Results 1 – 1 of 1) sorted by relevance
| /openbmc/u-boot/arch/arm/mach-exynos/ |
| H A D | dmc_init_ddr3.c | 38 struct exynos5_phy_control *phy0_ctrl, *phy1_ctrl; in ddr3_mem_ctrl_init() local
42 phy0_ctrl = (struct exynos5_phy_control *)samsung_get_base_dmc_phy(); in ddr3_mem_ctrl_init()
55 writel(val, &phy0_ctrl->phy_con39); in ddr3_mem_ctrl_init()
61 writel(val, &phy0_ctrl->phy_con42); in ddr3_mem_ctrl_init()
65 if (dmc_config_zq(mem, &phy0_ctrl->phy_con16, &phy1_ctrl->phy_con16, in ddr3_mem_ctrl_init()
66 &phy0_ctrl->phy_con17, &phy1_ctrl->phy_con17)) in ddr3_mem_ctrl_init()
70 writel(mem->phy0_pulld_dqs, &phy0_ctrl->phy_con14); in ddr3_mem_ctrl_init()
80 writel(mem->phy0_dqs, &phy0_ctrl->phy_con4); in ddr3_mem_ctrl_init()
83 writel(mem->phy0_dq, &phy0_ctrl->phy_con6); in ddr3_mem_ctrl_init()
86 writel(mem->phy0_tFS, &phy0_ctrl->phy_con10); in ddr3_mem_ctrl_init()
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