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Searched refs:per_pll_cntr2clk (Results 1 – 2 of 2) sorted by relevance

/openbmc/u-boot/arch/arm/mach-socfpga/include/mach/
H A Dclock_manager_s10.h50 u32 per_pll_cntr2clk; member
/openbmc/u-boot/arch/arm/mach-socfpga/
H A Dclock_manager_s10.c147 writel(cfg->per_pll_cntr2clk, &clock_manager_base->per_pll.cntr2clk); in cm_basic_init()