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Searched refs:opp_cnt (Results 1 – 17 of 17) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn314/
H A Ddcn314_hwseq.c73 int opp_cnt) in calc_mpc_flow_ctrl_cnt() argument
78 if (opp_cnt >= 2) in calc_mpc_flow_ctrl_cnt()
89 if (opp_cnt == 4) in calc_mpc_flow_ctrl_cnt()
100 int opp_cnt = 1; in update_dsc_on_stream() local
104 opp_cnt++; in update_dsc_on_stream()
112 …am->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt; in update_dsc_on_stream()
118 ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0); in update_dsc_on_stream()
119 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; in update_dsc_on_stream()
130 dsc_cfg.dc_dsc_cfg.num_slices_h *= opp_cnt; in update_dsc_on_stream()
131 dsc_cfg.pic_width *= opp_cnt; in update_dsc_on_stream()
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H A Ddcn314_optc.c50 static void optc314_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt, in optc314_set_odm_combine() argument
56 int mpcc_hactive = h_active / opp_cnt; in optc314_set_odm_combine()
65 if (opp_cnt == 4) { in optc314_set_odm_combine()
84 if (opp_cnt == 2) { in optc314_set_odm_combine()
89 } else if (opp_cnt == 4) { in optc314_set_odm_combine()
102 OTG_H_TIMING_DIV_MODE, opp_cnt - 1); in optc314_set_odm_combine()
103 optc1->opp_count = opp_cnt; in optc314_set_odm_combine()
H A Ddcn314_dio_stream_encoder.c303 if (is_two_pixels_per_containter(&param->timing) || param->opp_cnt > 1) { in enc314_stream_encoder_dp_unblank()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_optc.c218 void optc3_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt, in optc3_set_odm_combine() argument
223 / opp_cnt; in optc3_set_odm_combine()
234 ASSERT(opp_cnt == 2 || opp_cnt == 4); in optc3_set_odm_combine()
239 if (opp_cnt == 2) { in optc3_set_odm_combine()
244 } else if (opp_cnt == 4) { in optc3_set_odm_combine()
255 if (opp_cnt == 2) { in optc3_set_odm_combine()
260 } else if (opp_cnt == 4) { in optc3_set_odm_combine()
272 REG_SET(OTG_H_TIMING_CNTL, 0, OTG_H_TIMING_DIV_MODE, opp_cnt - 1); in optc3_set_odm_combine()
273 optc1->opp_count = opp_cnt; in optc3_set_odm_combine()
H A Ddcn30_optc.h354 void optc3_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt,
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn31/
H A Ddcn31_optc.c43 static void optc31_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt, in optc31_set_odm_combine() argument
48 / opp_cnt; in optc31_set_odm_combine()
53 if (opp_cnt == 4) { in optc31_set_odm_combine()
73 if (opp_cnt == 2) { in optc31_set_odm_combine()
78 } else if (opp_cnt == 4) { in optc31_set_odm_combine()
90 REG_SET(OTG_H_TIMING_CNTL, 0, OTG_H_TIMING_DIV_MODE, opp_cnt - 1); in optc31_set_odm_combine()
91 optc1->opp_count = opp_cnt; in optc31_set_odm_combine()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn32/
H A Ddcn32_optc.c45 static void optc32_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt, in optc32_set_odm_combine() argument
51 int mpcc_hactive = h_active / opp_cnt; in optc32_set_odm_combine()
60 if (opp_cnt == 4) { in optc32_set_odm_combine()
79 if (opp_cnt == 2) { in optc32_set_odm_combine()
84 } else if (opp_cnt == 4) { in optc32_set_odm_combine()
97 OTG_H_TIMING_DIV_MODE, opp_cnt - 1); in optc32_set_odm_combine()
98 optc1->opp_count = opp_cnt; in optc32_set_odm_combine()
H A Ddcn32_hwseq.c981 int opp_cnt) in calc_mpc_flow_ctrl_cnt() argument
986 if (opp_cnt >= 2) in calc_mpc_flow_ctrl_cnt()
997 if (opp_cnt == 4) in calc_mpc_flow_ctrl_cnt()
1008 int opp_cnt = 1; in update_dsc_on_stream() local
1012 opp_cnt++; in update_dsc_on_stream()
1020 …am->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt; in update_dsc_on_stream()
1026 ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0); in update_dsc_on_stream()
1027 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; in update_dsc_on_stream()
1038 dsc_cfg.dc_dsc_cfg.num_slices_h *= opp_cnt; in update_dsc_on_stream()
1039 dsc_cfg.pic_width *= opp_cnt; in update_dsc_on_stream()
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H A Ddcn32_dio_stream_encoder.c293 if (is_two_pixels_per_containter(&param->timing) || param->opp_cnt > 1 in enc32_stream_encoder_dp_unblank()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_optc.c188 void optc2_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt, in optc2_set_odm_combine() argument
193 / opp_cnt; in optc2_set_odm_combine()
196 ASSERT(opp_cnt == 2); in optc2_set_odm_combine()
226 optc1->opp_count = opp_cnt; in optc2_set_odm_combine()
H A Ddcn20_hwseq.c649 int opp_cnt) in calc_mpc_flow_ctrl_cnt() argument
654 if (opp_cnt >= 2) in calc_mpc_flow_ctrl_cnt()
665 if (opp_cnt == 4) in calc_mpc_flow_ctrl_cnt()
681 int opp_cnt = 1; in dcn20_enable_stream_timing() local
709 opp_inst[opp_cnt] = odm_pipe->stream_res.opp->inst; in dcn20_enable_stream_timing()
710 opp_cnt++; in dcn20_enable_stream_timing()
713 if (opp_cnt > 1) in dcn20_enable_stream_timing()
716 opp_inst, opp_cnt, in dcn20_enable_stream_timing()
754 rate_control_2x_pclk = rate_control_2x_pclk || opp_cnt > 1; in dcn20_enable_stream_timing()
757 flow_control.flow_ctrl_cnt1 = calc_mpc_flow_ctrl_cnt(stream, opp_cnt); in dcn20_enable_stream_timing()
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H A Ddcn20_optc.h107 void optc2_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt,
H A Ddcn20_resource.c1224 int opp_cnt = 1; in get_pixel_clock_parameters() local
1231 opp_cnt++; in get_pixel_clock_parameters()
1254 if (opp_cnt == 4) in get_pixel_clock_parameters()
1256 else if (optc2_is_two_pixels_per_containter(&stream->timing) || opp_cnt == 2) in get_pixel_clock_parameters()
1668 int opp_cnt = 1; in dcn20_validate_dsc() local
1671 opp_cnt++; in dcn20_validate_dsc()
1678 + stream->timing.h_border_right) / opp_cnt; in dcn20_validate_dsc()
1685 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; in dcn20_validate_dsc()
H A Ddcn20_stream_encoder.c482 if (is_two_pixels_per_containter(&param->timing) || param->opp_cnt > 1) { in enc2_stream_encoder_dp_unblank()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/inc/hw/
H A Dstream_encoder.h101 int opp_cnt; member
H A Dtiming_generator.h310 void (*set_odm_combine)(struct timing_generator *optc, int *opp_id, int opp_cnt,
/openbmc/linux/drivers/gpu/drm/amd/display/dc/link/
H A Dlink_dpms.c780 int opp_cnt = 1; in link_set_dsc_on_stream() local
784 opp_cnt++; in link_set_dsc_on_stream()
792 …am->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt; in link_set_dsc_on_stream()
798 ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0); in link_set_dsc_on_stream()
799 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; in link_set_dsc_on_stream()
809 dsc_cfg.dc_dsc_cfg.num_slices_h *= opp_cnt; in link_set_dsc_on_stream()
810 dsc_cfg.pic_width *= opp_cnt; in link_set_dsc_on_stream()