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Searched refs:num_states (Results 1 – 25 of 51) sorted by relevance

123

/openbmc/linux/drivers/gpu/drm/amd/display/dc/dml/dcn302/
H A Ddcn302_fpu.c126 .num_states = 1,
198 unsigned int num_states = 0; in dcn302_fpu_update_bw_bounding_box() local
282 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { in dcn302_fpu_update_bw_bounding_box()
284 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; in dcn302_fpu_update_bw_bounding_box()
285 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; in dcn302_fpu_update_bw_bounding_box()
288 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; in dcn302_fpu_update_bw_bounding_box()
289 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16; in dcn302_fpu_update_bw_bounding_box()
296 while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) { in dcn302_fpu_update_bw_bounding_box()
297 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; in dcn302_fpu_update_bw_bounding_box()
298 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; in dcn302_fpu_update_bw_bounding_box()
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dml/dcn303/
H A Ddcn303_fpu.c125 .num_states = 1,
194 unsigned int num_states = 0; in dcn303_fpu_update_bw_bounding_box() local
276 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { in dcn303_fpu_update_bw_bounding_box()
278 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; in dcn303_fpu_update_bw_bounding_box()
279 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; in dcn303_fpu_update_bw_bounding_box()
282 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; in dcn303_fpu_update_bw_bounding_box()
283 dram_speed_mts[num_states++] = in dcn303_fpu_update_bw_bounding_box()
291 while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) { in dcn303_fpu_update_bw_bounding_box()
292 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; in dcn303_fpu_update_bw_bounding_box()
293 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; in dcn303_fpu_update_bw_bounding_box()
[all …]
/openbmc/linux/arch/powerpc/kernel/
H A Drtas-proc.c508 int num_states = 0; in ppc_rtas_process_sensor() local
517 num_states = sizeof(key_switch) / sizeof(char *); in ppc_rtas_process_sensor()
518 if (state < num_states) { in ppc_rtas_process_sensor()
525 num_states = sizeof(enclosure_switch) / sizeof(char *); in ppc_rtas_process_sensor()
526 if (state < num_states) { in ppc_rtas_process_sensor()
538 num_states = sizeof(lid_status) / sizeof(char *); in ppc_rtas_process_sensor()
539 if (state < num_states) { in ppc_rtas_process_sensor()
546 num_states = sizeof(power_source) / sizeof(char *); in ppc_rtas_process_sensor()
547 if (state < num_states) { in ppc_rtas_process_sensor()
558 num_states = sizeof(battery_remaining) / sizeof(char *); in ppc_rtas_process_sensor()
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dml/dcn321/
H A Ddcn321_fpu.c122 .num_states = 1,
696 unsigned int i = 0, j = 0, num_states = 0; in dcn321_update_bw_bounding_box_fpu() local
767 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { in dcn321_update_bw_bounding_box_fpu()
769 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; in dcn321_update_bw_bounding_box_fpu()
770 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; in dcn321_update_bw_bounding_box_fpu()
773 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; in dcn321_update_bw_bounding_box_fpu()
774 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16; in dcn321_update_bw_bounding_box_fpu()
781 while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) { in dcn321_update_bw_bounding_box_fpu()
782 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; in dcn321_update_bw_bounding_box_fpu()
783 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; in dcn321_update_bw_bounding_box_fpu()
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dml/dcn301/
H A Ddcn301_fpu.c212 .num_states = 5,
301 ASSERT(vlevel < dml->soc.num_states); in calculate_wm_set_for_vlevel()
343 for (closest_clk_lvl = 0, j = dcn3_01_soc.num_states - 1; j >= 0; j--) { in dcn301_update_bw_bounding_box()
368 dcn3_01_soc.num_states = clk_table->num_entries; in dcn301_update_bw_bounding_box()
370 s[dcn3_01_soc.num_states] = in dcn301_update_bw_bounding_box()
371 dcn3_01_soc.clock_limits[dcn3_01_soc.num_states - 1]; in dcn301_update_bw_bounding_box()
372 s[dcn3_01_soc.num_states].state = dcn3_01_soc.num_states; in dcn301_update_bw_bounding_box()
/openbmc/linux/drivers/regulator/
H A Dirq_helpers.c62 num_rdevs = rid->num_states; in regulator_notifier_isr_work()
167 num_rdevs = rid->num_states; in regulator_notifier_isr()
291 h->rdata.num_states = rdev_amount; in init_rdev_state()
308 for (i = 0; i < h->rdata.num_states; i++) in init_rdev_errors()
430 if (WARN_ON(rid->num_states != 1 || hweight32(err) != 1)) in regulator_irq_map_event_simple()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/
H A Ddcn32_fpu.c133 .num_states = 1,
287 if (vlevel < context->bw_ctx.dml.vba.soc.num_states && in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch()
387 context->bw_ctx.dml.soc.clock_limits[context->bw_ctx.dml.soc.num_states - 1].dispclk_mhz, in dcn32_predict_pipe_split()
388 context->bw_ctx.dml.soc.clock_limits[context->bw_ctx.dml.soc.num_states - 1].dispclk_mhz, in dcn32_predict_pipe_split()
428 …else if (clk_frequency > context->bw_ctx.dml.soc.clock_limits[context->bw_ctx.dml.soc.num_states -… in dcn32_predict_pipe_split()
1178 if (*vlevel < context->bw_ctx.dml.soc.num_states) { in dcn32_full_validate_bw_helper()
1192 (*vlevel == context->bw_ctx.dml.soc.num_states || in dcn32_full_validate_bw_helper()
1218 if (*vlevel == context->bw_ctx.dml.soc.num_states && in dcn32_full_validate_bw_helper()
1242 for (i = *vlevel; i < context->bw_ctx.dml.soc.num_states; i++) { in dcn32_full_validate_bw_helper()
1249 if (*vlevel < context->bw_ctx.dml.soc.num_states in dcn32_full_validate_bw_helper()
[all …]
H A Ddisplay_mode_vba_32.c112 mode_lib->vba.MaxDppclk[v->soc.num_states - 1])); in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1654 start_state = v->soc.num_states - 1; in mode_support_configuration()
1658 for (i = v->soc.num_states - 1; i >= start_state; i--) { in mode_support_configuration()
1705 || i == v->soc.num_states - 1) in mode_support_configuration()
1710 || i == v->soc.num_states - 1 in mode_support_configuration()
1712 && (!mode_lib->vba.FCLKChangeRequirementFinal || i == v->soc.num_states - 1 in mode_support_configuration()
1741 start_state = v->soc.num_states - 1; in dml32_ModeSupportAndSystemConfigurationFull()
2033 for (i = start_state; i < v->soc.num_states; i++) { in dml32_ModeSupportAndSystemConfigurationFull()
2048 mode_lib->vba.MaxDispclk[v->soc.num_states - 1], in dml32_ModeSupportAndSystemConfigurationFull()
2071 mode_lib->vba.MaxDispclk[v->soc.num_states - 1], in dml32_ModeSupportAndSystemConfigurationFull()
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_resource.c1669 if (vlevel < context->bw_ctx.dml.soc.num_states) in dcn30_internal_validate_bw()
1673 (fast_validate || vlevel == context->bw_ctx.dml.soc.num_states || in dcn30_internal_validate_bw()
1686 if (vlevel < context->bw_ctx.dml.soc.num_states) { in dcn30_internal_validate_bw()
1695 if (vlevel == context->bw_ctx.dml.soc.num_states) in dcn30_internal_validate_bw()
1862 vba->ValidationStatus[vba->soc.num_states] = DML_FAIL_DSC_VALIDATION_FAILURE; in dcn30_internal_validate_bw()
2079 …_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states])); in dcn30_validate_bandwidth()
2095 unsigned int num_states = 0; in dcn30_update_bw_bounding_box() local
2177 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) { in dcn30_update_bw_bounding_box()
2179 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; in dcn30_update_bw_bounding_box()
2180 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++]; in dcn30_update_bw_bounding_box()
[all …]
/openbmc/linux/net/netfilter/ipvs/
H A Dip_vs_proto_ah_esp.c119 .num_states = 1,
141 .num_states = 1,
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/
H A Ddcn31_fpu.c169 .num_states = 5,
413 .num_states = 5,
611 for (closest_clk_lvl = 0, j = dcn3_1_soc.num_states - 1; j >= 0; j--) { in dcn31_update_bw_bounding_box()
643 dcn3_1_soc.num_states = clk_table->num_entries; in dcn31_update_bw_bounding_box()
704 dcn3_15_soc.num_states = clk_table->num_entries; in dcn315_update_bw_bounding_box()
750 for (closest_clk_lvl = 0, j = dcn3_16_soc.num_states - 1; j >= 0; j--) { in dcn316_update_bw_bounding_box()
760 closest_clk_lvl = dcn3_16_soc.num_states - 1; in dcn316_update_bw_bounding_box()
795 dcn3_16_soc.num_states = clk_table->num_entries; in dcn316_update_bw_bounding_box()
H A Ddisplay_mode_vba_31.c2131 v->soc.clock_limits[v->soc.num_states - 1].dispclk_mhz,
4071 for (i = 0; i < v->soc.num_states; i++) {
4081 && v->MaxDispclk[i] == v->MaxDispclk[v->soc.num_states - 1]
4082 && v->MaxDppclk[i] == v->MaxDppclk[v->soc.num_states - 1])) {
4089 && v->MaxDispclk[i] == v->MaxDispclk[v->soc.num_states - 1]
4090 && v->MaxDppclk[i] == v->MaxDppclk[v->soc.num_states - 1])) {
4097 && v->MaxDispclk[i] == v->MaxDispclk[v->soc.num_states - 1]
4098 && v->MaxDppclk[i] == v->MaxDppclk[v->soc.num_states - 1])) {
4232 if (!(v->MaxDispclk[i] == v->MaxDispclk[v->soc.num_states - 1]
4233 && v->MaxDppclk[i] == v->MaxDppclk[v->soc.num_states - 1])) {
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dml/dcn314/
H A Ddcn314_fpu.c150 .num_states = 5,
217 for (closest_clk_lvl = 0, j = dcn3_14_soc.num_states - 1; j >= 0; j--) { in dcn314_update_bw_bounding_box_fpu()
225 closest_clk_lvl = dcn3_14_soc.num_states - 1; in dcn314_update_bw_bounding_box_fpu()
259 dcn3_14_soc.num_states = clk_table->num_entries; in dcn314_update_bw_bounding_box_fpu()
H A Ddisplay_mode_vba_314.c2152 v->soc.clock_limits[v->soc.num_states - 1].dispclk_mhz,
4163 for (i = 0; i < v->soc.num_states; i++) {
4173 && v->MaxDispclk[i] == v->MaxDispclk[v->soc.num_states - 1]
4174 && v->MaxDppclk[i] == v->MaxDppclk[v->soc.num_states - 1])) {
4181 && v->MaxDispclk[i] == v->MaxDispclk[v->soc.num_states - 1]
4182 && v->MaxDppclk[i] == v->MaxDppclk[v->soc.num_states - 1])) {
4189 && v->MaxDispclk[i] == v->MaxDispclk[v->soc.num_states - 1]
4190 && v->MaxDppclk[i] == v->MaxDppclk[v->soc.num_states - 1])) {
4321 if (!(v->MaxDispclk[i] == v->MaxDispclk[v->soc.num_states - 1]
4322 && v->MaxDppclk[i] == v->MaxDppclk[v->soc.num_states - 1])) {
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/
H A Ddcn20_fpu.c289 .num_states = 5,
400 .num_states = 5,
511 .num_states = 5,
762 .num_states = 8
1843 unsigned int num_states) in dcn20_update_bounding_box() argument
1851 if (num_states == 0) in dcn20_update_bounding_box()
1867 for (i = 0; i < num_states; i++) { in dcn20_update_bounding_box()
1898 bb->num_states = num_calculated_states; in dcn20_update_bounding_box()
1902 bb->clock_limits[num_calculated_states].state = bb->num_states; in dcn20_update_bounding_box()
1913 for (i = 0; i < bb->num_states; i++) { in dcn20_cap_soc_clocks()
[all …]
H A Ddcn20_fpu.h61 unsigned int num_states);
H A Ddisplay_mode_vba_20.c1260 mode_lib->vba.soc.clock_limits[mode_lib->vba.soc.num_states].dispclk_mhz, in dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2598 for (k = 0; k <= mode_lib->vba.soc.num_states; k++) in dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
3441 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml20_ModeSupportAndSystemConfigurationFull()
3523 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml20_ModeSupportAndSystemConfigurationFull()
3874 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml20_ModeSupportAndSystemConfigurationFull()
3889 && i == mode_lib->vba.soc.num_states) in dml20_ModeSupportAndSystemConfigurationFull()
3896 && i == mode_lib->vba.soc.num_states) in dml20_ModeSupportAndSystemConfigurationFull()
3970 if (i != mode_lib->vba.soc.num_states) { in dml20_ModeSupportAndSystemConfigurationFull()
4002 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml20_ModeSupportAndSystemConfigurationFull()
4019 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml20_ModeSupportAndSystemConfigurationFull()
[all …]
H A Ddisplay_mode_vba_20v2.c1320 mode_lib->vba.soc.clock_limits[mode_lib->vba.soc.num_states].dispclk_mhz, in dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2671 for (k = 0; k <= mode_lib->vba.soc.num_states; k++) in dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
3548 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml20v2_ModeSupportAndSystemConfigurationFull()
3630 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml20v2_ModeSupportAndSystemConfigurationFull()
3981 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml20v2_ModeSupportAndSystemConfigurationFull()
3983 mode_lib->vba.MaxDispclk[mode_lib->vba.soc.num_states], in dml20v2_ModeSupportAndSystemConfigurationFull()
4000 && i == mode_lib->vba.soc.num_states) in dml20v2_ModeSupportAndSystemConfigurationFull()
4007 && i == mode_lib->vba.soc.num_states) in dml20v2_ModeSupportAndSystemConfigurationFull()
4084 if (i != mode_lib->vba.soc.num_states) { in dml20v2_ModeSupportAndSystemConfigurationFull()
4116 for (i = 0; i <= mode_lib->vba.soc.num_states; i++) { in dml20v2_ModeSupportAndSystemConfigurationFull()
[all …]
/openbmc/u-boot/arch/x86/include/asm/
H A Dspeedstep.h74 int num_states; member
/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_socbb.h78 uint32_t num_states; member
/openbmc/qemu/target/xtensa/
H A Dxtensa-isa.c251 malloc(isa->num_states * sizeof(xtensa_lookup_entry)); in xtensa_isa_init()
253 for (n = 0; n < isa->num_states; n++) { in xtensa_isa_init()
257 qsort(isa->state_lookup_table, isa->num_states, in xtensa_isa_init()
419 return intisa->num_states; in xtensa_isa_num_pipe_stages()
447 return intisa->num_states; in xtensa_isa_num_states()
1428 if ((ST) < 0 || (ST) >= (INTISA)->num_states) { \
1447 if (intisa->num_states != 0) { in xtensa_state_lookup()
1450 intisa->num_states, sizeof(xtensa_lookup_entry), in xtensa_state_lookup()
H A Dxtensa-isa-internal.h196 int num_states; member
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_resource.c1896 for (vlevel_split = vlevel; vlevel <= context->bw_ctx.dml.soc.num_states; vlevel++) in dcn20_validate_apply_pipe_split_flags()
1901 if (vlevel > context->bw_ctx.dml.soc.num_states) in dcn20_validate_apply_pipe_split_flags()
2051 if (vlevel > context->bw_ctx.dml.soc.num_states) in dcn20_fast_validate_bw()
2124 context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] = in dcn20_fast_validate_bw()
2345 unsigned int num_states = 0; in init_soc_bounding_box() local
2352 (&pool->base.pp_smu->nv_funcs.pp_smu, uclk_states, &num_states); in init_soc_bounding_box()
2367 if (clock_limits_available && uclk_states_available && num_states) { in init_soc_bounding_box()
2369 dcn20_update_bounding_box(dc, loaded_bb, &max_clocks, uclk_states, num_states); in init_soc_bounding_box()
2567 if (loaded_bb->num_states == 1) { in dcn20_resource_construct()
2575 } else if (loaded_bb->num_states > 1) { in dcn20_resource_construct()
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/
H A Ddm_pp_smu.h229 unsigned int *clock_values_in_khz, unsigned int *num_states);
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dml/dcn30/
H A Ddisplay_mode_vba_30.c1990 v->soc.clock_limits[mode_lib->soc.num_states - 1].dispclk_mhz, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
3854 for (i = 0; i < v->soc.num_states; i++) { in dml30_ModeSupportAndSystemConfigurationFull()
3863 …utODMCombine >= v->MaxDispclk[i] && v->MaxDispclk[i] == v->MaxDispclk[mode_lib->soc.num_states - 1] in dml30_ModeSupportAndSystemConfigurationFull()
3864 && v->MaxDppclk[i] == v->MaxDppclk[mode_lib->soc.num_states - 1])) { in dml30_ModeSupportAndSystemConfigurationFull()
3869 …MCombine2To1 >= v->MaxDispclk[i] && v->MaxDispclk[i] == v->MaxDispclk[mode_lib->soc.num_states - 1] in dml30_ModeSupportAndSystemConfigurationFull()
3870 && v->MaxDppclk[i] == v->MaxDppclk[mode_lib->soc.num_states - 1])) { in dml30_ModeSupportAndSystemConfigurationFull()
3875 …MCombine4To1 >= v->MaxDispclk[i] && v->MaxDispclk[i] == v->MaxDispclk[mode_lib->soc.num_states - 1] in dml30_ModeSupportAndSystemConfigurationFull()
3876 && v->MaxDppclk[i] == v->MaxDppclk[mode_lib->soc.num_states - 1])) { in dml30_ModeSupportAndSystemConfigurationFull()
3984 …(v->MaxDispclk[i] == v->MaxDispclk[v->soc.num_states - 1] && v->MaxDppclk[i] == v->MaxDppclk[v->so… in dml30_ModeSupportAndSystemConfigurationFull()
4010 for (i = 0; i < v->soc.num_states; i++) { in dml30_ModeSupportAndSystemConfigurationFull()
[all …]

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