| /openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/ |
| H A D | rv1_clk_mgr.c | 42 … int rv1_determine_dppclk_threshold(struct clk_mgr_internal *clk_mgr, struct dc_clocks *new_clocks) in rv1_determine_dppclk_threshold() argument
44 bool request_dpp_div = new_clocks->dispclk_khz > new_clocks->dppclk_khz; in rv1_determine_dppclk_threshold()
45 bool dispclk_increase = new_clocks->dispclk_khz > clk_mgr->base.clks.dispclk_khz; in rv1_determine_dppclk_threshold()
46 int disp_clk_threshold = new_clocks->max_supported_dppclk_khz; in rv1_determine_dppclk_threshold()
53 return new_clocks->dispclk_khz; in rv1_determine_dppclk_threshold()
58 if (new_clocks->dispclk_khz <= disp_clk_threshold) in rv1_determine_dppclk_threshold()
59 return new_clocks->dispclk_khz; in rv1_determine_dppclk_threshold()
63 return new_clocks->dispclk_khz; in rv1_determine_dppclk_threshold()
72 return new_clocks->dispclk_khz; in rv1_determine_dppclk_threshold()
78 return new_clocks->dispclk_khz; in rv1_determine_dppclk_threshold()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/ |
| H A D | dcn201_clk_mgr.c | 91 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; in dcn201_update_clocks() local
112 if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, clk_mgr_base->clks.phyclk_khz)) in dcn201_update_clocks()
113 clk_mgr_base->clks.phyclk_khz = new_clocks->phyclk_khz; in dcn201_update_clocks()
116 new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > (dc->debug.force_min_dcfclk_mhz * 1000)) ? in dcn201_update_clocks()
117 new_clocks->dcfclk_khz : (dc->debug.force_min_dcfclk_mhz * 1000); in dcn201_update_clocks()
119 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) in dcn201_update_clocks()
120 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz; in dcn201_update_clocks()
123 new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) in dcn201_update_clocks()
124 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz; in dcn201_update_clocks()
126 if (should_set_clock(safe_to_lower, new_clocks->socclk_khz, clk_mgr_base->clks.socclk_khz)) in dcn201_update_clocks()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/ |
| H A D | dcn20_clk_mgr.c | 221 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; in dcn2_update_clocks() local
259 new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > (dc->debug.force_min_dcfclk_mhz * 1000)) ? in dcn2_update_clocks()
260 new_clocks->dcfclk_khz : (dc->debug.force_min_dcfclk_mhz * 1000); in dcn2_update_clocks()
262 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) { in dcn2_update_clocks()
263 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz; in dcn2_update_clocks()
269 new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) { in dcn2_update_clocks()
270 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz; in dcn2_update_clocks()
275 if (should_set_clock(safe_to_lower, new_clocks->socclk_khz, clk_mgr_base->clks.socclk_khz)) { in dcn2_update_clocks()
276 clk_mgr_base->clks.socclk_khz = new_clocks->socclk_khz; in dcn2_update_clocks()
282 p_state_change_support = new_clocks->p_state_change_support || (total_plane_count == 0); in dcn2_update_clocks()
[all …]
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/ |
| H A D | dcn32_clk_mgr.c | 276 …id dcn32_update_dppclk_dispclk_freq(struct clk_mgr_internal *clk_mgr, struct dc_clocks *new_clocks) in dcn32_update_dppclk_dispclk_freq() argument
281 if (new_clocks->dppclk_khz) { in dcn32_update_dppclk_dispclk_freq()
283 * clk_mgr->base.dentist_vco_freq_khz / new_clocks->dppclk_khz; in dcn32_update_dppclk_dispclk_freq()
284 …new_clocks->dppclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR * clk_mgr->base.dentist_vco_freq_khz)… in dcn32_update_dppclk_dispclk_freq()
286 if (new_clocks->dispclk_khz > 0) { in dcn32_update_dppclk_dispclk_freq()
288 * clk_mgr->base.dentist_vco_freq_khz / new_clocks->dispclk_khz; in dcn32_update_dppclk_dispclk_freq()
289 …new_clocks->dispclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR * clk_mgr->base.dentist_vco_freq_khz… in dcn32_update_dppclk_dispclk_freq()
459 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; in dcn32_update_clocks() local
496 fclk_p_state_change_support = new_clocks->fclk_p_state_change_support; in dcn32_update_clocks()
510 new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > (dc->debug.force_min_dcfclk_mhz * 1000)) ? in dcn32_update_clocks()
[all …]
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/ |
| H A D | dcn30_clk_mgr.c | 197 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; in dcn3_update_clocks() local
231 new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > (dc->debug.force_min_dcfclk_mhz * 1000)) ? in dcn3_update_clocks()
232 new_clocks->dcfclk_khz : (dc->debug.force_min_dcfclk_mhz * 1000); in dcn3_update_clocks()
234 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) { in dcn3_update_clocks()
235 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz; in dcn3_update_clocks()
239 …if (should_set_clock(safe_to_lower, new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_d… in dcn3_update_clocks()
240 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz; in dcn3_update_clocks()
244 if (should_set_clock(safe_to_lower, new_clocks->socclk_khz, clk_mgr_base->clks.socclk_khz)) in dcn3_update_clocks()
246 clk_mgr_base->clks.socclk_khz = new_clocks->socclk_khz; in dcn3_update_clocks()
249 p_state_change_support = new_clocks->p_state_change_support; in dcn3_update_clocks()
[all …]
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/ |
| H A D | dcn31_clk_mgr.c | 139 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; in dcn31_update_clocks() local
154 if (new_clocks->zstate_support != DCN_ZSTATE_SUPPORT_DISALLOW && in dcn31_update_clocks()
155 new_clocks->zstate_support != clk_mgr_base->clks.zstate_support) { in dcn31_update_clocks()
156 dcn31_smu_set_zstate_support(clk_mgr, new_clocks->zstate_support); in dcn31_update_clocks()
158 clk_mgr_base->clks.zstate_support = new_clocks->zstate_support; in dcn31_update_clocks()
161 if (clk_mgr_base->clks.dtbclk_en && !new_clocks->dtbclk_en) { in dcn31_update_clocks()
163 clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en; in dcn31_update_clocks()
180 if (new_clocks->zstate_support == DCN_ZSTATE_SUPPORT_DISALLOW && in dcn31_update_clocks()
181 new_clocks->zstate_support != clk_mgr_base->clks.zstate_support) { in dcn31_update_clocks()
184 clk_mgr_base->clks.zstate_support = new_clocks->zstate_support; in dcn31_update_clocks()
[all …]
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/ |
| H A D | dcn316_clk_mgr.c | 141 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; in dcn316_update_clocks() local
155 clk_mgr_base->clks.zstate_support = new_clocks->zstate_support; in dcn316_update_clocks()
157 if (clk_mgr_base->clks.dtbclk_en && !new_clocks->dtbclk_en) { in dcn316_update_clocks()
159 clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en; in dcn316_update_clocks()
176 if (!clk_mgr_base->clks.dtbclk_en && new_clocks->dtbclk_en) { in dcn316_update_clocks()
178 clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en; in dcn316_update_clocks()
190 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) { in dcn316_update_clocks()
191 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz; in dcn316_update_clocks()
196 new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) { in dcn316_update_clocks()
197 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz; in dcn316_update_clocks()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/ |
| H A D | dcn315_clk_mgr.c | 131 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; in dcn315_update_clocks() local
141 clk_mgr_base->clks.zstate_support = new_clocks->zstate_support; in dcn315_update_clocks()
146 clk_mgr_base->clks.zstate_support = new_clocks->zstate_support; in dcn315_update_clocks()
148 if (clk_mgr_base->clks.dtbclk_en && !new_clocks->dtbclk_en) { in dcn315_update_clocks()
150 clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en; in dcn315_update_clocks()
167 if (!clk_mgr_base->clks.dtbclk_en && new_clocks->dtbclk_en) { in dcn315_update_clocks()
169 clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en; in dcn315_update_clocks()
181 if (!new_clocks->p_state_change_support) in dcn315_update_clocks()
182 new_clocks->dcfclk_khz = UNSUPPORTED_DCFCLK; in dcn315_update_clocks()
183 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) { in dcn315_update_clocks()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/ |
| H A D | dcn314_clk_mgr.c | 166 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; in dcn314_update_clocks() local
181 if (new_clocks->zstate_support != DCN_ZSTATE_SUPPORT_DISALLOW && in dcn314_update_clocks()
182 new_clocks->zstate_support != clk_mgr_base->clks.zstate_support) { in dcn314_update_clocks()
183 dcn314_smu_set_zstate_support(clk_mgr, new_clocks->zstate_support); in dcn314_update_clocks()
185 clk_mgr_base->clks.zstate_support = new_clocks->zstate_support; in dcn314_update_clocks()
188 if (clk_mgr_base->clks.dtbclk_en && !new_clocks->dtbclk_en) { in dcn314_update_clocks()
190 clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en; in dcn314_update_clocks()
207 if (new_clocks->zstate_support == DCN_ZSTATE_SUPPORT_DISALLOW && in dcn314_update_clocks()
208 new_clocks->zstate_support != clk_mgr_base->clks.zstate_support) { in dcn314_update_clocks()
211 clk_mgr_base->clks.zstate_support = new_clocks->zstate_support; in dcn314_update_clocks()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/ |
| H A D | rn_clk_mgr.c | 136 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; in rn_update_clocks() local
174 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) { in rn_update_clocks()
175 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz; in rn_update_clocks()
180 new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) { in rn_update_clocks()
181 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz; in rn_update_clocks()
187 if (new_clocks->dppclk_khz < 100000 && new_clocks->dppclk_khz > 0) in rn_update_clocks()
188 new_clocks->dppclk_khz = 100000; in rn_update_clocks()
194 if (new_clocks->dppclk_khz == 0 || new_clocks->dispclk_khz == 0) { in rn_update_clocks()
195 new_clocks->dppclk_khz = clk_mgr_base->clks.dppclk_khz; in rn_update_clocks()
196 new_clocks->dispclk_khz = clk_mgr_base->clks.dispclk_khz; in rn_update_clocks()
[all …]
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/ |
| H A D | vg_clk_mgr.c | 100 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; in vg_update_clocks() local
142 …if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz) && !dc-… in vg_update_clocks()
143 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz; in vg_update_clocks()
148 …new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz) && !dc->debug.disable… in vg_update_clocks()
149 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz; in vg_update_clocks()
154 if (new_clocks->dppclk_khz < 100000) in vg_update_clocks()
155 new_clocks->dppclk_khz = 100000; in vg_update_clocks()
157 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) { in vg_update_clocks()
158 if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz) in vg_update_clocks()
160 clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz; in vg_update_clocks()
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| /openbmc/linux/sound/isa/ |
| H A D | es18xx.c | 354 static const struct snd_ratnum new_clocks[2] = { variable
371 .rats = new_clocks,
402 if (runtime->rate_num == new_clocks[0].num) in snd_es18xx_rate_set()
|