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Searched refs:nand0_clk_cfg (Results 1 – 8 of 8) sorted by relevance

/openbmc/u-boot/arch/arm/include/asm/arch-sunxi/
H A Dclock_sun9i.h46 u32 nand0_clk_cfg; /* 0x400 nand0 clock configuration0 */ member
H A Dclock_sun8i_a83t.h45 u32 nand0_clk_cfg; /* 0x80 nand clock control */ member
H A Dclock_sun4i.h41 u32 nand0_clk_cfg; /* 0x80 nand sub clock control */ member
H A Dclock_sun50i_h6.h137 u32 nand0_clk_cfg; /* 0x810 NAND0 clock control */ member
H A Dclock_sun6i.h44 u32 nand0_clk_cfg; /* 0x80 nand0 clock control */ member
/openbmc/u-boot/drivers/mtd/nand/raw/
H A Dsunxi_nand_spl.c547 clrbits_le32(&ccm->nand0_clk_cfg, CCM_NAND_CTRL_ENABLE | AHB_DIV_1); in nand_deselect()
H A Dsunxi_nand.c304 &ccm->nand0_clk_cfg); in sunxi_nfc_set_clk_rate()
/openbmc/u-boot/board/sunxi/
H A Dboard.c360 setbits_le32(&ccm->nand0_clk_cfg, CCM_NAND_CTRL_ENABLE | AHB_DIV_1); in nand_clock_setup()