Searched refs:nand0_clk_cfg (Results 1 – 8 of 8) sorted by relevance
46 u32 nand0_clk_cfg; /* 0x400 nand0 clock configuration0 */ member
45 u32 nand0_clk_cfg; /* 0x80 nand clock control */ member
41 u32 nand0_clk_cfg; /* 0x80 nand sub clock control */ member
137 u32 nand0_clk_cfg; /* 0x810 NAND0 clock control */ member
44 u32 nand0_clk_cfg; /* 0x80 nand0 clock control */ member
547 clrbits_le32(&ccm->nand0_clk_cfg, CCM_NAND_CTRL_ENABLE | AHB_DIV_1); in nand_deselect()
304 &ccm->nand0_clk_cfg); in sunxi_nfc_set_clk_rate()
360 setbits_le32(&ccm->nand0_clk_cfg, CCM_NAND_CTRL_ENABLE | AHB_DIV_1); in nand_clock_setup()