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Searched refs:n_lock_w_phy0 (Results 1 – 1 of 1) sorted by relevance

/openbmc/u-boot/arch/arm/mach-exynos/
H A Ddmc_init_ddr3.c450 uint32_t val, n_lock_r, n_lock_w_phy0, n_lock_w_phy1; in ddr3_mem_ctrl_init() local
710 n_lock_w_phy0 = (lock0_info & CTRL_LOCK_COARSE_MASK) >> 2; in ddr3_mem_ctrl_init()
713 n_lock_r |= n_lock_w_phy0; in ddr3_mem_ctrl_init()
787 writel((val + n_lock_w_phy0), &phy0_ctrl->phy_con12); in ddr3_mem_ctrl_init()